William Stallings Computer Organization and Architecture sixth Edition

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Data/Output Problems. Wide assortment of peripheralsDelivering distinctive measures of dataAt diverse speedsIn diverse formatsAll slower than CPU and RAMNeed I/O modules w/some

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´╗┐William Stallings Computer Organization and Architecture 6 th Edition Chapter 7 Input/Output (amended 10/15/02)

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Input/Output Problems Wide assortment of peripherals Delivering diverse measures of information At various speeds In various arrangements All slower than CPU and RAM Need I/O modules w/some "insight"

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Input/Output Module Interface to CPU and Memory Interface to at least one peripherals

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Generic Model of I/O Module

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External Devices Human lucid (human interface) Monitor, printer, console, mouse Machine comprehensible Disk, tape, sensors Communication Modem Network Interface Card (NIC)

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External Device Block Diagram

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I/O Module Function Control & Timing CPU (Processor) Communication Device Communication Data Buffering Error Detection (e.g., additional equality bit)

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I/O Steps CPU checks (cross examines) I/O module gadget status I/O module returns status If prepared, CPU asks for information exchange by sending an order to the I/O module I/O module gets a unit of information (byte, word, and so forth.) from gadget I/O module exchanges information to CPU Variations of these means for yield, DMA, and so on

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Processor/gadget Communications Command translating Data Status announcing Address acknowledgment

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Need for Data Buffering: Typical I/O Data Rates

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I/O Module Diagram

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I/O Module Decisions Hide or uncover gadget properties to CPU Support different or single gadget Control gadget capacities or leave for CPU Also O/S choices e.g. Unix regards all that it can as a document

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Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)

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Programmed I/O CPU has coordinate control over I/O Sensing status Read/compose orders Transferring information CPU sits tight for I/O module to finish operation Wastes CPU time

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Programmed I/O - detail CPU asks for I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits occasionally I/O module does not educate CPU specifically I/O module does not interfere with CPU may hold up or return later

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I/O Commands CPU issues address Identifies module (& gadget if >1 per module) CPU issues charge Control - guiding module e.g. turn up circle Test - check status e.g. control? Blunder? Perused/Write Module exchanges information by means of support from/to gadget

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Addressing I/O Devices Under modified I/O information exchange is exceptionally similar to memory get to (CPU perspective) Each gadget given remarkable identifier CPU orders contain identifier (address)

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I/O Mapping Memory mapped I/O Devices and memory share an address space I/O looks simply like memory read/compose No uncommon charges for I/O Large determination of memory get to summons accessible Isolated I/O Separate address spaces Need I/O or memory select lines Special orders for I/O Limited set

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Interrupt Driven I/O Overcomes CPU holding up No rehashed CPU checking of gadget I/O module hinders when prepared

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Interrupt Driven I/O Basic Operation CPU issues read charge I/O module gets information from fringe while CPU does other work I/O module intrudes on CPU asks for information I/O module exchanges information

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CPU Viewpoint Issue read summon Do other work Check for hinder at end of every guideline cycle If interfered with:- Save setting (registers) Process interfere with Fetch information & store See Operating Systems notes

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Design Issues How would you distinguish the module issuing the intrude? How would you manage different interferes? i.e. an interfere with handler being intruded on

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Identifying Interrupting Module (1) Different line for every module PC Limits number of gadgets Software survey CPU asks every module thus Slow

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Identifying Interrupting Module (2) Daisy Chain or Hardware survey Interrupt Acknowledge sent down a chain Module capable spots vector on transport CPU utilizes vector to recognize handler routine Bus Master Module must claim the transport before it can raise hinder e.g. PCI & SCSI

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Multiple Interrupts Each intrude on line has a need Higher need lines can interfere with lower need lines If transport acing just current ace can intrude

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Example - PC Bus 80x86 has one intrude on line 8086 based frameworks utilize one 8259A intrude on controller 8259A has 8 intrude on lines

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Sequence of Events 8259A acknowledges interferes with 8259A decides need 8259A signs 8086 (raises INTR line) CPU Acknowledges 8259A puts amend vector on information transport CPU forms interfere

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ISA Bus Interrupt System ISA transport chains two 8259As together Link is by means of interfere with 2 Gives 15 lines 16 lines less one for connection IRQ 9 is utilized to re-course anything attempting to utilize IRQ 2 Backwards similarity Incorporated in chip set

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82C59A Interrupt Controller

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Intel 82C55A Programmable Peripheral Interface

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Using 82C55A To Control Keyboard/Display

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Direct Memory Access Interrupt driven and customized I/O require dynamic CPU intercession Transfer rate is constrained CPU is tied up DMA is the appropriate response

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DMA Function Additional Module (equipment) on transport DMA controller assumes control from CPU for I/O

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DMA Module Diagram

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DMA Operation CPU reveals to DMA controller:- Read/Write Device address Starting location of memory square for information Amount of information to be exchanged CPU continues with other work DMA controller manages exchange DMA controller sends hinder when completed

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DMA Transfer Cycle Stealing DMA controller assumes control transport for a cycle Transfer of single word of information Not an interfere with CPU does not switch setting CPU suspended just before it gets to transport i.e. prior to an operand or information bring or an information record Slows CPU yet not as much as CPU doing exchange

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Aside What impact does storing memory have on DMA? Imply: what amount are the framework transports accessible?

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DMA Configurations (1) Single Bus, Detached DMA controller Each exchange utilizes transport twice I/O to DMA then DMA to memory CPU is suspended twice

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DMA Configurations (2) Single Bus, Integrated DMA Controller may bolster >1 gadget Each exchange utilizes transport once DMA to memory CPU is suspended once

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DMA Configurations (3) Separate I/O Bus underpins all DMA empowered gadgets Each exchange utilizes transport once DMA to memory CPU is suspended once

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I/O Channels I/O gadgets getting more complex e.g. 3D illustrations cards CPU educates I/O controller to do exchange I/O controller does whole exchange Improves speed Takes stack off CPU Dedicated processor is quicker

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I/O Channel Architecture

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Interfacing Connecting gadgets together Bit of wire? Committed processor/memory/transports? E.g. FireWire, InfiniBand

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IEEE 1394 FireWire High execution serial transport Fast Low cost Easy to actualize Also being utilized as a part of computerized cameras, VCRs and TV

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FireWire Configuration Daisy fasten Up to 63 gadgets on single port Really 64 of which one is the interface itself Up to 1022 transports can be associated with scaffolds Automatic arrangement No transport eliminators May be tree structure

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Simple FireWire Configuration

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FireWire 3 Layer Stack Physical Transmission medium, electrical and flagging qualities Link Transmission of information in bundles Transaction Request-reaction convention

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FireWire Protocol Stack

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FireWire - Physical Layer Data rates from 25 to 400Mbps Two types of discretion Based on tree structure Root goes about as authority First start things out served Natural need controls synchronous solicitations i.e. who is closest to root Fair mediation Urgent intervention

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FireWire - Link Layer Two transmission sorts Asynchronous Variable measure of information and a few bytes of exchange information exchanged as a bundle To unequivocal address Acknowledgment returned Isochronous Variable measure of information in succession of settled size parcels at customary interims Simplified tending to No affirmation

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FireWire Subactions

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InfiniBand I/O determination went for top of the line servers Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel) Version 1 discharged mid 2001 Architecture and spec. for information stream amongst processor and astute I/O gadgets Intended to supplant PCI in servers Increased limit, expandability, adaptability

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InfiniBand Architecture Remote stockpiling, systems administration and association between servers Attach servers, remote stockpiling, arrange gadgets to focal texture of switches and connections Greater server thickness Scalable server farm Independent hubs included as required I/O separate from server up to 17m utilizing copper 300m multimode fiber optic 10km single mode fiber Up to 30Gbps

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InfiniBand Switch Fabric

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InfiniBand Operation 16 consistent channels (virtual paths) per physical connection One path for administration, rest for information Data in stream of bundles Virtual path devoted briefly to end to end exchange Switch maps activity from approaching to active path

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InfiniBand Protocol Stack

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Foreground Reading Check out Universal Serial Bus (USB) Compare with other correspondence norms e.g. Ethernet

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