# Verilog II CPSC 321

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﻿Verilog II CPSC 321 Andreas Klappenecker

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Modules module mod_name (parameters); input … yield … reg … endmodule

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Full Adder module fulladd(cin, x, y, s, cout) input cin, x, y; yield s, cout; allot s = x ^ y ^ cin; allocate cout = (x & y) | (cin & x) | (cin & y); endmodule

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Full Adder module fulladd(cin, x,y,s, cout); input cin, x, y; yield s, cout; appoint { cout, s } = x + y + cin; endmodule The dole out proclamation relegates the MSB to cout and the LSB to s.

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Hello World module best; starting \$display("Hello, world!"); endmodule beginning articulations are executed once by the test system

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Vector wires Range [msb: lsb] wire [3:0] S; S = 4'b0011 The consequence of this task is S[3] = 0, S[2] = 0, S[1] = 1, S[0] = 1 wire [1:2] A; A = S[2:1]; implies A[1] = S[2], A[2] = S[1]

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Variables come in two flavors reg numbers reg can demonstrate combinatorial or successive parts of the circuits reg does not really indicate an enlist! Whole numbers regularly utilized as circle control factors helpful for depicting the conduct of a module

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Simple Example module testgate; reg b, c;/factors wire a, d, e;/nets and (d, b, c);/entryways or (e, d, c);/nand(a, e, b);/starting start/reproduced once b=1; c=0;/blocking assignments #10 \$display("a = %b", an); end endmodule What esteem will be printed?

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Operators 1's supplement ~A 2's supplement - A bitwise AND A&B lessening &A produces AND of all bits in A Concatenate {a,b,c} | {a,b,c} = a | b | c Replication administrators 2{A} = {A,A} {2{A},3{B}} = {A,A,B,B,B}

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Continuous assignments Single piece assignments allot s = x ^ y ^ cin; dole out cout = (x & y) | (cin & x) | (cin &y ) Multibit assignments wire [1:3] a,b,c; … allocate c = a & b;

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Always Blocks A dependably square contains at least one procedural proclamations dependably @(sensitivity list) dependably @(x or y) start s = x ^ y; c = x & y; end

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Mux: Structural Verilog module mux(f, a,b,sel); input a,b,sel; yield f; wire f1, f2; not(nsel, sel); and(f1, a,nsel); and(f2, b, sel); or (f, f1, f2); endmodule b f a sel

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Mux: Dataflow Model module mux2(f, a,b,sel); output f; input a,b,sel; relegate f = (a & ~sel) | (b & sel); endmodule

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Mux: Behavioral Model module mux2(f, a,b,sel); output f; input a,b,sel; reg f; always @(a or b or sel) if (sel==1) f = b; else f = an; endmodule

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Sign expansion and expansion module adder_sign(x,y,s,ss); input [3:0] x,y; yield [7:0] s, ss; dole out s = x + y, ss = {{4{x[3]}},x}+{{4{y[3]},y} endmodule x = 0011, y = 1101 s = 0011 + 1101 = 00010000 ss = 0011 + 1101 = 00000011 + 11111101= 00000000

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Demux Example 2-to-4 demultiplexer with dynamic low

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Demux: Structural Model/2-to-4 demultiplexer module demux1(z,a,b,enable); input a,b,enable; yield [3:0] z; wire abar,bbar; not v0(abar,a), v1(bbar,b); nand (z[0],enable,abar,bbar); nand (z[1],enable,a,bbar); nand (z[2],enable,abar,b); nand (z[3],enable,a,b); endmodule

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Demux: Dataflow show/2-to-4 demux/dataflow demonstrate module demux2(z,a,b,enable); input a,b,enable; yield [3:0] z; appoint z[0] = | {~enable,a,b}; dole out z[1] = ~(enable & a & ~b); dole out z[2] = ~(enable & ~a & b); dole out z[3] = empower ? ~(a & b) : 1'b1; endmodule

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Demux: Behavioral Model/2-to-4 demultiplexer with dynamic low yields module demux3(z,a,b,enable); input a,b,enable; yield [3:0] z; reg z;/not by any stretch of the imagination an enlist! continuously @(a or b or empower) case ({enable,a,b}) default: z = 4'b1111; 3'b100: z = 4'b1110; 3'b110: z = 4'b1101; 3'b101: z = 4'b1011; 3'b111: z = 4'b0111; endcase endmodule

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Always Blocks The affectability list @( … ) contains the occasions setting off an assessment of the piece @(a or b or c) @(posedge a) @(negedge b) A Verilog compiler assesses the announcements in the dependably hinder in the request in which they are composed

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Assignments If a variable is allocated an esteem in a blocking task a = b & c; then resulting references to a contain the new estimation of a Non-blocking assignments <= doles out the esteem that the factors had while entering the dependably square

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D Flip-slump module D_FF(Q,D,clock); yield Q; input D, clock; reg Q; dependably @(negedge clock) Q <= D; endmodule

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Clock A consecutive circuit will require a clock provided by the testbed Clock code section reg clock; parameter period = 100; introductory clock 0; dependably @(period/2) clock = ~clock;

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D-Flipflop with Synchronous Reset module flipflop(D, Clock, Resetn, Q); input D, Clock, Resetn; yield Q; reg Q; dependably @(posedge Clock) if (!Resetn) Q <= 0; else Q <= D; endmodule/7.46 in [BV]

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Gated D-Latch module latch(D, clk, Q) input D, clk; yield Q; reg Q; dependably @(D or clk) if (clk) Q <= D; endmodule Missing else proviso => a hook will be integrated to keep estimation of Q when clk=0

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Shift Register: What isn't right here? module example(D,Clock, Q1, Q2) input D, Clock; yield Q1, Q2; reg Q1, Q2; dependably @(posedge Clock) start end endmodule Q1 = D; Q2 = Q1; Q1 = D; Q2 = Q1;/D=Q1=Q2

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Shift enlist: Correct Version module example(D,Clock, Q1, Q2) input D, Clock; yield Q1, Q2; reg Q1, Q2; dependably @(posedge Clock) start Q1 <= D; Q2 <= Q1; end endmodule

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Rule of Thumb Blocking assignments are utilized to portray combinatorial circuits Non-blocking assignments are utilized as a part of consecutive circuits

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n-bit Ripple Carry Adder module ripple(cin, X, Y, S, cout); parameter n = 4; input cin; input [n-1:0] X, Y; yield [n-1:0] S; yield cout; reg [n-1:0] S; reg [n:0] C; reg cout; whole number k; dependably @(X or Y or cin) start C[0] = cin; for(k = 0; k <= n-1; k=k+1) start S[k] = X[k]^Y[k]^C[k]; C[k+1] = (X[k] & Y[k]) |(C[k]&X[k])|(C[k]&Y[k]); end cout = C[n]; end endmodule

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Loops and Integers The for circle is utilized to instantiate equipment modules The number k essentially monitors instantiated equipment Do not mistake numbers for reg factors

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Bit-Counter Count the quantity of bits having esteem 1 in enlist X Again a case for parameters Another case of a for circle

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Bit Counter module bit_cnt(X,Count); parameter n = 4; parameter logn = 2; input [n-1:0] X; yield [logn:0] Count; reg [logn:0] Count; whole number k; dependably @(X) start Count = 0; for(k=0;k<n;k= k+1) Count=Count+X[k]; end endmodule

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Blocks of Procedural Code introductory executed once toward the start of reenactment beginning \$display("Hello World"); dependably over and over executed start end successive execution of square explanations postpones include fork-join pieces simultaneous execution of articulations

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Concurrency Example module concurrency_example; starting start #1 \$display("Block 1 stmt 1"); \$display("Block 1 stmt 2"); #2 \$display("Block 1 stmt 3"); end introductory start \$display("Block 2 stmt 1"); #2 \$display("Block 2 stmt 2"); #2 \$display("Block 2 stmt 3"); end endmodule Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt 2 Block 2 stmt 2 Block 1 stmt 3 Block 2 stmt 3

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Concurrency Example module concurrency_example; beginning start #1 \$display("Block 1 stmt 1"); \$display("Block 1 stmt 2"); #2 \$display("Block 1 stmt 3"); end beginning start \$display("Block 2 stmt 1"); #2 \$display("Block 2 stmt 2"); #2 \$display("Block 2 stmt 3"); end endmodule Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt 2 Block 2 stmt 2 Block 1 stmt 3 Block 2 stmt 3

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Concurrency: fork and join module concurrency_example; starting fork #1 \$display("Block 1 stmt 1"); \$display("Block 1 stmt 2"); #2 \$display("Block 1 stmt 3"); join beginning fork \$display("Block 2 stmt 1"); #2 \$display("Block 2 stmt 2"); #2 \$display("Block 2 stmt 3"); join endmodule Block 1 stmt 2 Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt 3 Block 2 stmt 2 Block 2 stmt 3

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Displaying Results a = 4'b0011 \$display("The estimation of an is %b", a); The estimation of an is 0011 \$display("The estimation of an is %0b", a); The estimation of an is 11 If you \$display to print an esteem that is changing amid this time step, then you may get the new or the old esteem; utilize \$strobe to get the new esteem

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Displaying Results Standard showing capacities \$display, \$write, \$strobe, \$monitor Writing to a record rather than stdout \$fdisplay, \$fwrite, \$fstrobe, \$fmonitor Format specifiers %b, %0b, %d, %0d, %h, %0h, %c, %s,…

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Display Example module f1; whole number f; beginning start f = \$fopen("myFile"); \$fdisplay(f, "Hello, bla bla"); end endmodule

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Moore Machines The yield of a Moore machine depends just on the present state. Yield rationale and next state rationale are infrequently blended. next state rationale display state enlist yield rationale input

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Coding Moore Machines The rationale in the Moore machine can be portrayed by two case proclamations (one case articulation if rationale pieces are combined) Enumerate every conceivable condition of information and current state, and produce the outpu