The Role of Programmable DSPs in 3G Handsets Chaitali Sengupta February, 2002

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Diagram. 3G Wireless StandardsFunctional perspective of 3GPP FDD-DS (WCDMA)Complexity analysisMapping to architectureSystem outline philosophy. Remote Cellular Systems. . . . . . . Spine Network. IS-95, GSM, IS-136 third Gen. (W-CDMA,

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The Role of Programmable DSPs in 3G Handsets Chaitali Sengupta February, 2002

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Overview 3G Wireless Standards Functional perspective of 3GPP FDD-DS (WCDMA) Complexity examination Mapping to engineering System outline procedure

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Wireless Cellular Systems IS-95, GSM, IS-136 third Gen. (W-CDMA, … ..) Backbone Network PSTN ISDN

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Today's Market % 2G - Today 2.5G - 2001 3G - 2003+ 9% PDC J-WCDMA GSM 66% W-CDMA GPRS IS136 EDGE 10% CDMA2000 IS95 15% IS95B 3G Wireless Standards Focus: 3GPP FDD Direct Sequence Mode (WCDMA)

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Parameters characterizing the FDD-DS (WCDMA) 3G standard Parameter Description/esteem Carrier dispersing 5 MHz Physical edge length 10ms Spreading element 2 k , k=2-8 : UL, 2 k , k=2-9: DL Channel coding Convolutional and Turbo Multirate Variable spreading/multicode Diversity methods Multiple Tx radio wires, Multipath Maximum information rates 384Kbps/2Mbps 3GPP FDD-DS mode

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Handset beat level MMI PROTOCOL STACK ARM APPLICATION TASKS L1 SW DATA I/O L1 DBB HARDWARE DSP LCD, Camera, Etc. ABB RF

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WCDMA System Downlink CHANNEL CODING, INTERLEAVER, ETC client's bits SOURCE CODING ABB and RF SPREADING (BASE STATION) channel TRANSMITTER MRC (multipath and Tx assorted qualities) ABB and RF DEINTERLEAVER DESPREADER RATE MATCHING DPE AND FINGER ALLOCATION CHANNEL ESTIMATION VITERBI/TURBO (CHANNEL DECODER) TIME TRACKING FREQUENCY TRACKING CRC CHECK (MOBILE USER) VOCODER, APPLICATION, ETC AUTOMATIC GAIN CONTROL RECEIVER

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DBB Functional View DPE Finger alloc. DLL Viterbi I/Q information from A/D Despread MRC CCTrCH Turbo MAC (L2) de-figuring Ch. Est. AFC to ABB & RF vocoder AGC Protocol stack (information) applications control Measurements (neighbor & dynamic set) Search 1 Layer3 (RRC) and Protocol stack (control) Directed pursuit Set Maintenance RX Initial hunt applications figuring vocoder to D/A Spreading (Chip-level) CCTrCH handling TX MAC (L2)

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DBB Design Goals Power, control, control But: DBB is 10-25 % of aggregate handset control Flexibility Evolving norms Fine tuning in field Scalability Increasing information rates Fast outline cycle Cost

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Complexity Analysis Decoders Search/track Despread MRC A B C A: 8 Kbps voice just B: 12.2 Kbps voice + 384 Kbps information C: 2 Mbps information

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HW/SW parceling Processing necessities rely on upon: information rate, number of solid cells in the region, remote channel conditions, and so forth. Essential tradeoff: control versus adaptability Dedicated HW: Lowest power achievable for target capacities Lower adaptability to change SW preparing on low power DSPs Higher adaptability

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HW/SW dividing Category 1: Definitely in HW in the close term, Very high MIPS or information I/O necessities E.g. despreading Category 2: Definitely in SW Reasonable handling prerequisites Requires adaptability E.g. channel estimation Category 3: In HW or SW based Total power targets Service situations for a particular usage Maximal Ratio Combining (MRC)

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RX DPE Finger alloc. SW/HW DLL Viterbi I/Q information from A/D Despread MRC CCTrCH Turbo MAC (L2) de-figuring Ch. Est. AFC to ABB & RF vocoder AGC Protocol stack (information) applications control Measurements (neighbor & AS) Search 1 Layer3 (RRC) and Protocol stack (control) Directed hunt Set Maintenance Initial pursuit applications figuring vocoder to D/A Spreading (Chip-level) CCTrCH handling TX MAC (L2)

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Co-processor approach How to get adaptability at low power and cost? "approximately coupled" (LCC) and "firmly coupled" (TCC) coprocessors Based all things considered time to finish a "guideline" Find a DSP/coprocessor parcel that parities adaptability with a sensible MIPs level on the DSP. E.g., for Viterbi translating: the DSP could play out every one of the information preparing up to the branch metric era and a coprocessor could play out the staying high MIPS assignments of state metric refresh and follow back.

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Tightly coupled coprocessors TCC: errand finishes in the request of a couple guideline cycles Small measure of information handled per undertaking The DSP will solidify amid the operation of the TCC. TCC to principle processor correspondence regularly happens through enlist peruses and composes. E.g. bit control coprocessor Processors that permit direction set upgrade through equipment TCC units by method for a "Co-processor Port" ARM processor (the ARM7TDMI), and the TMS320C55x processor With time, the capacity of the TCC may relocate into the DSP

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Tightly coupled coprocessors Memory System T Instruction C decipher I/f TCC Register document TCC guidelines TMS320C55x

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Loosely coupled coprocessors LCC: Task will keep running in parallel to the DSP for some direction cycles before it requires more collaboration with the DSP. Takes care of the major issue of transport transmission capacity Computational units nearby to the information and masterminded particularly for the information get to required for a class of calculations. In time the LCC usefulness will move to the DSP: When DSP transport data transfer capacity and computational power is adequate. E.g. LCC for WCDMA chip rate handling (despreading, time following, way seek) Coprocessor can perform basic yet high MIPS undertakings DSP gives design (e.g. averaging length for way look) as a result the framework is completely programmable inside the space of WCDMA chip rate preparing.

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Loosely coupled coprocessors Address Generation chips from AFE Input cradle PN Generation Datapath Analog Front end (AFE) Controller & Counters Instruction cushion DSP/coprocessor interface Address Generation Output support SRAM DSP CORRELATOR COPROCESSOR

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Centralized v.s. Disseminated Architectures The WCDMA framework is parallel in nature Centralized approach: Resource sharing between capacities Centralized and more unpredictable control Lesser region Distributed approach Possibly lesser power as parts might be turned off when sit Less mind boggling control Most handy frameworks require a blend of both

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Handset best level MMI PROTOCOL STACK ARM APPLICATION TASKS L1 SW DATA I/O L1 DBB HARDWARE DSP LCD, Camera, Etc. ABB RF

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Control plane and Data handling Use of a DSP and smaller scale controller mix DSP is in charge of the substantial obligation flag preparing Control plane is separated between the DSP and the miniaturized scale controller. DSP regularly manages low dormancy hard ongoing capacities Micro-controller gives Centralized control of all physical layer assets Higher layers in the convention stack with diminishing continuous substance Texas Instruments OMAP TM engineering comprising of an ARM9 and a C55x processor.

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Modem and Applications Same stage or numerous? Issues: Development coordinations Protecting the constant way of the modem Type endorsement Power and cost obviously! Practically speaking there will conceivably be both sorts Separate stages: top of the line telephones, Single stage: low end principally voice and less requesting applications

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System Analysis Methodology How to oversee plan of such complex frameworks with such a large number of advancement criteria? Beat down strategy Characterization of use Control plane Data plane Characterization of engineering choices Abstract models of execution for quick recreations of use to design mapping.

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Summary 3G handset DBB has preparing prerequisites a few circumstances higher than 2G Power is the driving criteria took after by cost and adaptability Completely DSP SW handling is impractical Challenges: Choice of framework parceling Design of committed HW with adequate adaptability working with programmable DSPs Methodology to bolster such choices!

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Reference The Role of Programmable DSPs in Dual Mode (2G+3G) Handsets. C. Sengupta, N. Veau, S. Sriram, Z. Gu, P. Folacci, S. Kinjo. Book part in: The Application of Programmable DSPs in Mobile Communications . Editors: A. Gatherer and E. Auslander

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APPLICATION ARCHITECTURE Scenario (N) MAPPING Scenario (1) Components (e.g DSP center, peripherals, DMA) Platform Schedulers/rules (e.g. transport discretion strategies, DMA conventions, planning arrangements) Control plane Mapping alternatives Resource utilization (of process mapped to part; in MHz, memory, IO) Processes Control stream (messages) Data stream System consistent state Data plane SIMULATION (in VCC: information plane driven by control plane, no genuine information handling or information exchange ) PERFORMANCE (Total MHz, memory, I/O) Performance Simulation

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