The Improvement of Psec-Determination TDC for Vast Region TOF Frameworks

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Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC) ... Time Stretcher: Simulation Result. 1ns Time Interval (Input Signal) ...

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´╗┐The Development of Psec-Resolution TDC for Large Area TOF Systems Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake (ANL) Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)

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From H. Frisch Output at anode from recreation of 10 particles experiencing intertwined quartz window-T. Philosophy, R. Schroll Major advances for TOF estimations: Ability to reproduce hardware and frameworks to anticipate outline execution Jitter on driving edge 0.86 psec

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Requirement: Psec-Resolution TDC MCP_PMT Output Signal Start 500pS Reference Clock Stop Tw 1 ps Resolution Time-to-Digital Converter!!!

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Diagram of MCP-PMT Electronics From Harold

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Approaches & Possibilities (1) TAC-ADC 1/4 "Zero"- walk Disk. TAC Driver 11-bit ADC Receiver PMT 2 Ghz PLL REF_CLK 4x1Ghz PLL psFront-end (Timing Module Option #1)

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TAC-ADC: Simulation Result Electronics with commonplace entryway nerves << 1 psec

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Approaches & Possibilities (2) Time Stretcher 1/4 "Zero"- walk Disk. Stretcher Driver 11-bit Counter Receiver PMT CK5Ghz 2 Ghz PLL REF_CLK psFront-end (Timing Module Option #2)

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Time Stretcher: Simulation Result x200 Stretched Time Interval (Output Signal ) Stretched Time = 274ns (pedestal=74ns) 1ns Time Interval (Input Signal) 0 50ns 100ns 150ns 200ns 250ns 300ns

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VCO: Submission of Oct. 2006 Ultimate Goal: To assemble TDC with 1 pSec Resolution for Large Scale of Time-of-Flight Detector. Essential Goal: To fabricate 2-Ghz VCO, scratch module of PLL that produces the TDC reference flag Cycle-to-Cycle Time-jitter < 1 ps To assess IHP SG25H1/M4M5 Technology for our applications To pick up encounters on utilizing Cadence apparatuses (Virtuoso Analog Environment) Circuit Design (VSE) Simulation (Specter) Chip Layout (VLE, XLE, VCAR) DRC and LVS Check (Diva, Assura, Caliber) Parasitic Extraction (Diva) Post Layout Simulation (Specter) GDSII Stream out Validation Tape Out

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Diagram of Phase-Locked Loop CP F ref I 1 Uc PD VCO F 0 LF I 2 1N PD: Phase Detector CP: Charge Pump LF: Loop Filter VCO: Voltage Controlled Oscillator

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IHP (SG25H1) 0.25 m SiGe BiCMOS Technology 0.25 m BiCMOS innovation 200Ghz NPN HBT (hetero-intersection bipolar transistor) MIM Capacitors (layer2-layer3) ( 1f/1u 2 ) Inductors (layer3-layer4) High dielectric stack for RF detached segment 5 metal layers (Al) Digital Library: Developing

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SG25 Process Specification

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2-GHz BiCMOS VCO Schematic Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50 W Line Drivers

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V-F Plot (3 display cases @ 27C-55C) Frequency Temperature: 27C-55C Supply: VDD=2.5V VControl changed 0.18V VControl

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Phase Noise ( 3 show cases @ 27C) @100KHz counterbalance Worst Typical Best Temperature: 27C Supply: VDD=2.5V

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Calculation of Cycle-to-Cycle Jitter

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2-GHz VCO Performance Summary (1) T=27C f 0 = 2 GHz stage clamor: dBc/Hz@100K balance

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2-GHz VCO Performance Summary (2) T=55C f 0 = 2 GHz stage commotion: dBc/Hz@100K balance

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Virtuoso XL Layout View

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Virtuoso Chip Assembly Router View

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Diagram of Post Layout Simulation Schematic Analog_extracted

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Transit Analysis: Comparison of Schematic and Post Layout Simulations Outputs@50 W loads Schematic Post Layout

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V-F Plot: Comparison of Schematic and Post Layout Simulations Frequency Post Layout Schematic Vcontrol

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Phase Noise: Post Layout Simulations VDD=2.5V Temp.=27C, 55C Phase Noise @100KHZ balance

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Conclusion (1) VCO time-jitter met our prerequisite. (2) Post design reproduction coordinated schematic reenactment exceptionally well. (3) Some issues we have experienced with pcell library, design, DRC, LVS and auto-directing functionalities. (4) Ready for October Submission.

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