Stage Locked Loops

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Strife between freq determination and PLL data transmission/settling time. Since PFD is controlled by f_ref, consequently f_sampling = f_refFor security and exchange qualities, need f_ref to be 10\'s of times of PLL bandwidthHence, f_BW ~ 0.01 to 0.1 * f_refPLL settling time = k * 1/_BW. Expanding freq determination and BW.

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