Sister: A System for Sequential Circuit Synthesis

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Sister: A Framework for Successive Circuit Blend. An Instructional exercise of Utilization and Programming of Sister. Presentation. Berkeley: MIS II - > Sister: A Framework for Successive Circuit Blend Combinational rationale union Two level and multi-level rationale union Innovation mapping

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´╗┐Sister: A System for Sequential Circuit Synthesis A Tutorial of Usage and Programming of SIS UCLA CS258G

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Introduction Berkeley: MIS II - > SIS: A System for Sequential Circuit Synthesis Combinational rationale union Two level & multi-level rationale union Technology mapping Sequential Circuit Synthesis Verification UCLA CS258G

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Interactive Interface: Example $/u/class/CS258G/sister 1.3/container/sister sis> read_blif C1908.blif2 sis> print_stats C1908.iscas pi=33 po=25 nodes=400 latches= 0 lits(sop)= 800 sis> source script.rugged sis> print_stats C1908.iscas pi=33 po=25 nodes=152 latches= 0 lits(sop)= 553 sis> write_blif C1908_r.blif sis> quit UCLA CS258G

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SIS Commands utilized as a part of the case read_blif circuit1.blif Read blif-design circuit source script.rugged Do advancement utilizing an arrangement of orders many scripts in/u/class/CS258G/sister 1.3/sister/sis_lib write_blif circuit2.blif Write blif-organize circuit UCLA CS258G

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Some Other SIS Commands tech_decomp Decompose every one of the hubs in the present system into AND doors OR entryways or both read_eqn eqn_circuit Read eqn-arrange circuit check blif_circuit Verify whether the blif_circuit is indistinguishable with the one read in some time recently, which is eqn_circuit . print_stats Print details of the present circuit UCLA CS258G

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SIS Programming Two styles: Integrated programming style (having the capacity to include charges into existing SIS interface) Take favorable position of the SIS orders web based Running and troubleshooting should be done under SIS's interface. /u/class/CS258G/project_template/sis_guide.txt/u/class/CS258G/project_template/readme.txt Stand-alone programming style Only connection with SIS library Easier to run and investigate UCLA CS258G

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Directory Structure/u/class/CS258G/sister 1.3/SIS bundle area/u/class/CS258G/sister 1.3/canister/Executable SIS program Add it to your way settings/u/class/CS258G/proj_2004/circuits/Benchmark circuits/u/class/CS258G/project_template/programming layout for coordinated style/u/class/CS258G/proj_2004/scratch/UCLA RASP bundle executable/u/class/CS258G/instructional exercise/Contains this instructional exercise UCLA CS258G

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PI Node PO PI Node PO PI SIS Network PI: Primary Input PO: Primary Output, a unique hub with one info and no yield. Its capacity is the same as a cushion. Hub: Internal hub UCLA CS258G

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Input and Output: BLIF arrange BLIF organize: Berkeley Logic Interchange Format Used broadly in scholarly research work Function: Cubic frame (whole of item) Each hub has multi-information sources and single yield Benchmark circuit for this venture/u/class/CS258G/proj_2004/circuits/streamlined by script.algebraic Decomposed into 2-information AND doors as well as entryways UCLA CS258G

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Blif Example: C17.blif .demonstrate C17.iscas .inputs 1GAT[0] 2GAT[1] 3GAT[2] 6GAT[3] 7GAT[4] .yields 22GAT[10] 23GAT[9] .names 1GAT[0] 2GAT[1] 3GAT[2] [2] 22GAT[10] 1-1-1 - 1 .names 2GAT[1] 7GAT[4] [2] 23GAT[9] 1 - 11 1 .names 3GAT[2] 6GAT[3] [2] 0-1 - 0 1 .end UCLA CS258G

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Programming Example ( Makefile of Stand-alone Style) CC = gcc SIS =/u/class/CS258G/sister 1.3/sister PSRC = my_main.c my_util.c POBJ = $(PSRC:.c=.o) PHDR = my_main.h TARGET = my.x LIBS = $(SIS)/lib/libsis.a INCLUDE = - I$(SIS)/incorporate CFLAGS = - g $(INCLUDE) - DSIS LDFLAGS = - g $(TARGET): $(POBJ) $(LIBS) $(CC) $(LDFLAGS) - o $(TARGET) $(POBJ) $(LIBS) - lm UCLA CS258G

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Programming Example (C codes) #include "my_main.h" int blif_to_network ( scorch *filename, network_t **net ) { FILE *fp; fp=fopen( filename, "r"); read_blif( fp, net ) ; fclose( fp ); } int write_result( roast *filename, network_t *net ) { FILE *fp; fp=fopen( filename, "w"); write_blif(fp, net, 0, 0 ); fclose( fp ); } UCLA CS258G

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Programming Example (Con't) main(int argc, burn **argv) { init_sis(0); option(argc, argv); blif_to_network(mid_filename,&net1); dfs = network_dfs(net1); for(i1=0;i1<array_n(dfs);i1++){ node1 = array_fetch(node_t*, dfs, i1); if(node_type(node1)==PRIMARY_INPUT) proceed with; if(node_type(node1)==PRIMARY_OUTPUT) proceed; if(node_num_fanin(node1)==1) proceed; simplify_node(node1, SIM_METHOD_NOCOMP, SIM_DCTYPE_ALL, SIM_ACCEPT_SOP_LITS, SIM_FILTER_NONE); } network_sweep(net1); write_result(final_filename, net1); network_free(net1); } UCLA CS258G

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SIS Documents SIS paper/u/class/CS258G/sister 1.3/SIS_paper.ps The point by point presentation of SIS framework, including BLIF design portrayal Description of capacities/u/class/CS258G/sister 1.3/sister/doc/UCLA CS258G

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Commonly Used Documents network.doc depict organize operations. node.doc depict hub operations. array.doc depict the operations for exhibit information structure. st.doc portray the operations for st_table (hash table) io.doc depict the operations for I/O of SIS. util.doc depict some supporting operations for programming. UCLA CS258G

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Questions To Deming Chen demingc@cs.ucla.edu Check FAQ sometimes/u/class/CS258G/FAQ UCLA CS258G

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Stratix II ALM Overview High adaptability Implement complex rationale capacities with substantial info number Reduce rationale level Reduce directing use developed UCLA CS258G

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Stratix II ALM Overview High adaptability Implement complex rationale capacities with vast information number Reduce rationale level Reduce steering use augmented required UCLA CS258G

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ALM Normal Mode One ALM can execute the accompanying capacities with no limitations Any two 4-input capacities One 5-input capacity and one 3-input work One 6-input work UCLA CS258G

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ALM Normal Mode One ALM can actualize the accompanying capacities with sharing sources of info One 5-input capacity and one 4-input work that sharing one sources of info Two 5-input works that sharing two sources of info Two 6-input works that sharing 4 inputs UCLA CS258G

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Extended LUT mode One ALM can execute one 7-input work in the event that it can fit into the accompanying graph UCLA CS258G

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QUIP stream Verify the nature of the outlines through condition of-craftsmanship devices Quartus can take the QUIP interface to peruse in mapped circuits read in SIS organize mapping VQM dumper Quartus Quip interface UCLA CS258G

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Additional Notes Extra information fields in SIS information structure One ALM may contains two LUTs Pairing is expected to record the two LUTs in one ALM The "undef1" field in SIS can be utilized for such reason typedef struct { int mark; ... ... } proj_aux_t; API: PROJ_PAIR_ID(n) Remember to dispense the memory for the structure Example code in/u/class/CS258G/project_template/myproj/com_myproj.c UCLA CS258G

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