Semiconductor Memories

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Diagram. Idea/need of memory Parameters Types/arrangement Basic components Basic Cell circuits Peripheral hardware . Idea. Information stockpiling vital for processingBinary storageSwitchesHow do you execute this in Hardware?. Prerequisites. Simple readingEasy WritingHigh densitySpeed, more speed and still more speed.

Presentation Transcript

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Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal

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Outline Concept/need of memory Parameters Types/characterization Basic components Basic Cell circuits Peripheral hardware

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Concept Data stockpiling basic for preparing Binary stockpiling Switches How would you actualize this in Hardware?

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Requirements Easy perusing Easy Writing High thickness Speed, more speed and still more speed

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Memory Chip Configuration

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Semiconductor Memory Classification Non-Volatile Read-Write Memory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM

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RAM Random compose and read operation for any phone Volatile information Most of PC memory DRAM Low Cost High Density Medium Speed SRAM High Speed Ease of utilization Medium Cost

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ROM Non-unstable Data Method of Data Writing Mask ROM Data composed amid chip creation PROM Fuse ROM: Non-rewritable EPROM: Erase information by UV beams EEPROM: Erase and compose through electrical means Speed 2-3 times slower than RAM Upper utmost on compose operations Flash Memory – High thickness, Low Cost

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Basic Cells SRAM DRAM

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Bit Word M8 M9 M4 M5 CAM ••• CAM M6 M7 Word S Word int CAM ••• CAM M3 M2 Match M1 Wired-NOR Match Line Static CAM Memory Cell •••

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CAM in Cache Memory CAM SRAM ARRAY Hit Logic Address Decoder Input Drivers Sense Amps/Input Drivers Address Tag Hit R/W Data

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ROM EEPROM Fuse ROM Floating Gate

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MOS NAND ROM V DD Pull-up gadgets BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high naturally with exemption of chose column

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D G S Non-Volatile Memories The Floating-entryway transistor (FAMOS) Floating door Gate Source Drain t bull t bull + +_ n p Substrate Schematic image Device cross-area

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20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V - S D S D S D Avalanche infusion Removing programming voltage leaves charge caught Programming brings about higher V . T Floating-Gate Transistor Programming

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A "Programmable-Threshold" Transistor

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Periphery Decoders Sense Amplifiers Input/Output Buffers Control/Timing Circuitry

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Row Decoders Collection of 2 M complex rationale doors Organized in general and thick mold (N)AND Decoder NOR Decoder

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Hierarchical Decoders Multi-arrange usage enhances execution • WL 1 WL 0 An A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • NAND decoder utilizing 2-input pre-decoders An A 1 0 1 3 2 3

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D make V as little × D C V as conceivable t = - p I av huge little Sense Amplifiers Idea: Use Sense Amplifer little s.a. move input yield

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V (1) BL V PRE D V (1) V (0) t Sense amp initiated Word line actuated Sense Amp Operation

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Differential Sense Amplifier V DD M 3 4 y Out M bit 1 2 M SE 5 Directly pertinent to SRAMs

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Reliability and Yield

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References Digital Integrated Circuits, 2 nd Edition, Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm Sedra & Smith, Microelectronic Circuits, 4 th Edition, Chapter 13 Section 13.9, 13.10, 13.11, 13.12 VLSI Memory Chip Design, Kiyoo Itoh

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