Section 10. Memory, CPLDs, and FPGAs

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Part 10. Memory, CPLDs, and FPGAs

10.1 Read-Only Memory A read-just memory (ROM) is a combinational circuit with n data sources and b yields. (Fig. 10-1) A ROM stores reality table of a n-input, b-yield combinational rationale work. A decoder executed by ROM (Table 10-1, Fig. 10-2) ROM is a sort of non-unpredictable memory. A 4x4 multiplier actualized by ROM. (Table 10-3) Internal structure of A diode ROM. (Fig. 10-5) A ROM utilizing two-dimensional interpreting. (Fig. 10-7) Internal structure of a MOS transistor ROM (Fig. 10-8)

Commercial ROM sorts (Table 10-5) Mask ROM Programmable Read-Only Memory (PROM) Erasable Programmable Read-Only Memory (EPROM) Floating door innovation (Fig. 10-10) Programmed by applying a HIGH voltage on the non-drifting door, and deleted by presenting it to ultra-violet light. Electrically Erasable Programmable Read-Only Memory (EEPROM) Flash ROM Some standard ROMs (Fig. 10-11) Output Enable (OE) to control tri-state yields. Chip-Select (CS) to empower the ROM chip. Address translating of ROM applications (Fig. 10-12)

ROM for low power application (Fig. 10-13) ROM timing (Fig. 10-14) t AA : Access time from address. t ACS : Access time from chip select. t OE : Output Enable time. The proliferation delay from OE and CS both attested until the yield drivers have left the Hi-Z state. t OZ : Output-Disable Time t OH : Output-Hold time

10.2 Read/Write Memory RAM (Random Access Memory): most mainstream read/compose memory. The time it takes to peruse/compose a touch of memory is free of the bit's area. Static RAM (SRAM) Dynamic RAM (DRAM) SRAM and DRAM are both unpredictable. Ferroelectric RAM A sort of non-unstable RAMs.

10.3 Static RAM Basic structure of a SRAM (Fig. 10-19) Read operation Write operation Internal structure of a SRAM RAM cell (Fig. 10-20) A 8x4 SRAM timing Read timing (Fig. 10-22) t AA : Access time from address t ACS : Access time from chip select t OE : Output-Enable time t OZ : Output-Disable time t OH : Output-Hold time

Write timing (Fig. 10-23) t AS : Address setup time before compose t AH : Address hold time after compose t CSW : Chip-select setup before end of compose t WP : Write beat width t DS : Data setup time before end of compose t DH : Data hold time after end of compose WE - controlled compose versus CS - controlled compose (Fig. 10-23) Standard static RAMs (Fig. 10-24) Asynchronous SRAM and Synchronous SRAM

10.4 Dynamic RAM DRAM structure and operation A DRAM cell (Fig. 10-31) Write operation Setting the word line to 1. To store a 1, a HIGH voltage is set on the bit line, which charges the capacitor through the "on" transistor. To store a 0, a LOW voltage is set on the bit line, which releases the capacitor through the "on" transistor. Perused operation The bit line is initially precharged to a voltage somewhere between HIGH and LOW. The word line is set HIGH so that the precharged bit line is pulled marginally higher or somewhat lower. A sense speaker distinguishes this little change and recuperates a 1 or 0 in like manner.

Reading a DRAM cell annihilate the first voltage put away on the capacitor, the DRAM cell must be composed back the first information subsequent to perusing. Measure revive (Fig. 10-32) Internal structure of a 64Kx1 DRAM (Fig. 10-33) Multiplexed address inputs RAS_L : Row deliver strobe to store the higher request bits of the address into the column address enlist . CAS_L : Column deliver strobe to store the lower arrange bits of the address into the section address enroll . Push locks : the hooks used to store information input/yield from the memory exhibit. Measure timing RAS-just invigorate cycle timing (Fig. 10-34) Read cycle (Fig. 10-35) Write cycle (Fig. 10-36) Synchronous DRAM

10.5 Complex Programmable Logic Devices 10.6 Field-Programmable Gate Arrays (FPGA) Xilinx XC4000 FPGA family Configurable rationale square (CLB) (Fig. 10-44) Configurable interconnect structure (Fig. 10-46) CLB and wiring subtle elements (Fig. 10-47)