Part 7 Input

Presentation Transcript

Section 7 Input/Output HW: 7:13 & 7:18 Due Wed, 11/8/06

Input/Output Problems Wide assortment of peripherals Delivering distinctive measures of information At various speeds In various arrangements All slower than CPU and RAM Need I/O modules

Generic Model of I/O Module

I/O Module Function Support single or numerous gadgets Hide or uncover gadget properties Provides: Control & Timing CPU Communication Device Communication Data Buffering Error Detection

I/O Module Diagram

Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)

Programmed I/O CPU has coordinate control over I/O Sensing status Read/compose orders Transferring information CPU sits tight for I/O module to finish operation Usually not a decent utilization of CPU time

Programmed I/O - detail CPU asks for I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits occasionally CPU may hold up or return later

Interrupt driven I/O - CPU Viewpoint Issue I/O charge Do other work - Check for hinder at end of every guideline cycle When intrude on demand is conceded:- Save setting (registers) Process interfere with Execute "benefit schedule" Continue other work

Interrupt Driven I/O – Device Perspective CPU issues I/O summon (empower interfere with) I/O module gets information from fringe while CPU does other work I/O module interferes with CPU (Interrupt ask for) Device adjusted by CPU

DMA Function DMA controller(s) assumes control from CPU for I/O Additional Module(s) joined to transport

Typical DMA Module Diagram

DMA Operation CPU discloses to DMA controller:- Read/Write Device address Starting location of memory piece for information Amount of information to be exchanged CPU goes ahead with other work DMA controller manages exchange DMA controller sends hinder when completed

DMA Transfer Cycle Stealing DMA controller assumes control transport for a cycle Transfer of single word of information Not an intrude on CPU does not switch setting CPU suspended just before it gets to transport i.e. prior to an operand or information bring or an information record Slows CPU yet not as much as CPU doing exchange

DMA and Interrupt Breakpoints During an Instruction Cycle What isn't right with this?

Aside What impact does storing memory have on DMA? What impact uses of DRAMs have on DMA ?

DMA Configurations (1) Single Bus, Detached DMA controller Each exchange utilizes transport twice I/O to DMA then DMA to memory CPU is suspended twice

DMA Configurations (2) Single Bus, Integrated DMA Controller may bolster >1 gadget Each exchange utilizes transport once DMA to memory CPU is suspended once

DMA Configurations (3) Separate I/O Bus underpins all DMA empowered gadgets Each exchange utilizes transport once DMA to memory CPU is suspended once

I/O Channels I/O channels are processors devoted to I/O e.g. 3D design cards CPU teaches I/O controller to do exchange I/O controller does whole exchange from one or numerous gadgets Makes exchanges less obvious to CPU Improves speed Takes stack off CPU

I/O Channel Architecture

Interfacing Options Parallel - PCI - SCSI Serial - RS 232 Local Networks - Ethernet Newer advances -FireWire - InfiniBand -USB Wireless - BlueTooth - WiFi Automation - CAN

Intel 82C55A Programmable Peripheral Interface

Keyboard/Display Interfaces to 82C55A

Serial - RS 232 UART (Universal Asynchronous Receiver & Transmitter) Serial interface on a chip Historically extremely huge After 30 years, still a standard

RS232 Character transmission

UART Block Diagram

UART Application

Ethernet CSMA/CD (Carrier Sense Multiple Access/Collision Detection) A neighborhood get to technique in which conflict between at least two stations is settled by crash recognition. At the point when two stations transmit in the meantime, they both stop and flag a crash has happened. Every then tries again subsequent to holding up a foreordained day and age. To maintain a strategic distance from another crash, the stations included each pick an arbitrary time interim to plan the retransmission of the impacted edge. To ensure that the impact is perceived, Ethernet requires that a station must keep transmitting until the 50 microsecond period has finished. On the off chance that the station has under 64 bytes of information to send, then it must cushion the information by including zeros toward the end.

Bob Metcalf's Ethernet Concept - 1976

Network Reference demonstrate - Ethernet

Ethernet bundle

Ethernet square outline

Layering – Example: OSI Network Layers International Standards Organization's (ISO) Open Systems Interconnection (ISO) Model: The Physical Layer depicts the physical properties of the different interchanges media, and in addition the electrical properties and understanding of the traded signals. Case: this layer characterizes the span of Ethernet coaxial link, the sort of BNC connector utilized, and the end technique. The Data Link Layer portrays the legitimate association of information bits transmitted on a specific medium. Illustration: this layer characterizes the encircling, tending to and registration of Ethernet bundles. The Network Layer portrays how a progression of trades over different information connections can convey information between any two hubs in a system. Case: this layer characterizes the tending to and directing structure of the Internet. The Transport Layer depicts the quality and nature of the information conveyance. Illustration: this layer characterizes if and how retransmissions will be utilized to guarantee information conveyance. The Session Layer portrays the association of information groupings bigger than the parcels took care of by lower layers. Case: this layer depicts how demand and answer bundles are combined in a remote strategy call. The Presentation Layer depicts the linguistic structure of information being exchanged. Illustration: this layer portrays how coasting point numbers can be traded between hosts with various math positions. The Application Layer portrays how genuine function really completes. Illustration: this layer would execute document framework operations.

Simple Example OF 7 Layer OSI Model Application Layer : Set of C Instructions, Set of Data I0 I1 I2 … . IN Do D1 D2 … Dm Presentation Layer : ASCII Coding ASC I0 I1 I2 … . IN Do D1 D2 … Dm Session Layer : What handle at PC x is speaking with what prepare at PC y X4 Y6 ASC I0 I1 I2 … . IN Do D1 D2 … Dm Transport Layer : Guaranteed Transmission, successively numbered parcels of 4096 bytes GT4 P34 x4 Y6 ASC I0 I1 I2 … . IN Do D1 D2 … Dm PCKSUM Network Layer : Path through Network N23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 … . IN Do D1 D2 … Dm PCKSUM Data Link Layer : Serial 256 bytes for every casing STRT T(N23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 … . IN Do D1 D2 … Dm PCKSUM)CKSM Physical Layer : 9600Baud, Coax link

IEEE 1394 FireWire (Competitor to USB) High execution serial transport Fast Low cost Easy to actualize Also being utilized as a part of advanced cameras, VCRs and TV

FireWire Configuration Daisy affix Up to 63 gadgets on single port Really 64 of which one is the interface itself Up to 1022 transports can be associated with extensions Automatic design No transport eliminators May be tree structure

Simple FireWire Configuration

FireWire 3 Layer Stack Physical Transmission medium, electrical and flagging qualities Link Transmission of information in bundles Transaction Request-reaction convention

FireWire Protocol Stack

FireWire - Physical Layer Data rates from 25 to 400Mbps Two types of assertion Based on tree structure Root goes about as referee First start things out served Natural need controls concurrent solicitations i.e. who is closest to root Fair mediation Urgent intervention

FireWire - Link Layer Two transmission sorts Asynchronous Variable measure of information and a few bytes of exchange information exchanged as a parcel To express address Acknowledgment returned Isochronous Variable measure of information in arrangement of settled size bundles at standard interims Simplified tending to No affirmation

FireWire Subactions

InfiniBand I/O determination went for top of the line servers Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel) Version 1 discharged mid 2001 Architecture and spec. for information stream amongst processor and astute I/O gadgets Intended to supplant PCI in servers Increased limit, expandability, adaptability

InfiniBand Architecture Remote stockpiling, systems administration and association between servers Attach servers, remote stockpiling, arrange gadgets to focal texture of switches and connections Greater server thickness Scalable server farm Independent hubs included as required I/O separate from server up to 17m utilizing copper 300m multimode fiber optic 10km single mode fiber Up to 30Gbps

InfiniBand Switch Fabric

InfiniBand Operation 16 intelligent channels (virtual paths) per physical connection One path for administration, rest for information Data in stream of bundles Virtual path committed incidentally to end to end exchange Switch maps activity from approaching to active path

InfiniBand Protocol Stack