Part 4 Field-Effect Transistors

Chapter 4 field effect transistors
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Section 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock Microelectronic Circuit Design McGraw-Hill Chap4-1

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Chapter Goals Describe operation of MOSFETs and JFETs. Characterize FET attributes in operation areas of cutoff, triode and immersion. Create scientific models for i-v attributes of MOSFETs and JFETs. Present graphical representations for yield and exchange trademark depictions of electron gadgets. Characterize and differentiate qualities of improvement mode and exhaustion mode FETs. Characterize images to speak to FETs in circuit schematics. Examine circuits that inclination transistors into various working districts. Learn essential structure and veil format for MOS transistors and circuits. Investigate MOS gadget scaling Microelectronic Circuit Design McGraw-Hill Chap1-2

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Chapter Goals (contd.) Contrast 3 and 4 terminal gadget conduct. Descibe wellsprings of capacitance in MOSFETs and JFETs. Investigate FET displaying in SPICE . Microelectronic Circuit Design McGraw-Hill Chap1-3

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Types of Field-Effect Transistors MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) Primary componenet in high-thickness VLSI chips, for example, recollections and microchips JFET (Junction Field-Effect Transistor) Finds application particularly in simple and RF circuit outline Microelectronic Circuit Design McGraw-Hill Chap1-4

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MOS Capacitor Structure First anode Gate : Consists of low-resistivity material, for example, polycrystalline silicon Second terminal Substrate or Body: n - or p - sort semiconductor Dielectric-Silicon dioxide:stable amazing electrical cover amongst entryway and substrate. Microelectronic Circuit Design McGraw-Hill Chap1-5

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Substrate Conditions for Different Biases Accumulation V G <<V TN Depletion V G <V TN Inversion V G >V TN Microelectronic Circuit Design McGraw-Hill Chap1-6

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Low-recurrence C-V Characteristics for MOS Capacitor on P-sort Substrate MOS capacitance is non-straight capacity of voltage. Add up to capacitance in any district directed by the partition between capacitor plates. Add up to capacitance demonstrated as arrangement blend of settled oxide capacitance and voltage-subordinate exhaustion layer capacitance. Microelectronic Circuit Design McGraw-Hill Chap1-7

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NMOS Transistor: Structure 4 gadget terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and deplete areas frame pn intersections with substrate. v SB , v DS and v GS constantly positive amid ordinary operation. v SB dependably < v DS and v GS to switch inclination pn intersections Microelectronic Circuit Design McGraw-Hill Chap1-8

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NMOS Transistor: Qualitative I-V Behavior V GS <<V TN : Only little spillage current streams. V GS <V TN : Depletion locale framed under entryway converges with source and deplete consumption districts. No present streams amongst source and deplete. V GS >V TN : Channel framed amongst source and deplete. On the off chance that v DS >0,, limited i D streams from deplete to source. i B =0 and i G =0. Microelectronic Circuit Design McGraw-Hill Chap1-9

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NMOS Transistor: Triode Region Characteristics for where, K n = K n 'W/L K n '=μ n C bull "" (A/V 2 ) C bull ''=ε bull/T bull ε bull = oxide permittivity (F/cm) T ox= oxide thickness (cm) Microelectronic Circuit Design McGraw-Hill Chap1-10

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NMOS Transistor: Triode Region Characteristics (contd.) Output attributes have all the earmarks of being direct. FET acts like an entryway source voltage-controlled resistor amongst source and deplete with Microelectronic Circuit Design McGraw-Hill Chap1-11

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MOSFET as Voltage-Controlled Resistor Example 1: Voltage-Controlled Attenuator If K n =500μA/V 2 , V TN =1V, R =2kω and V GG =1.5V, then, If K n =500μA/V 2 , V TN =1V, R =2kω and V GG =1.5V, then, To keep up triode area operation, or Microelectronic Circuit Design McGraw-Hill Chap1-12

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MOSFET as Voltage-Controlled Resistor (contd.) Example 2: Voltage-Controlled High-Pass Filter Voltage Transfer work, where, cut-off recurrence If K n =500μA/V 2 , V TN =1V, C =0.02μF and V GG =1.5V, then, To keep up triode district operation, Microelectronic Circuit Design McGraw-Hill Chap1-13

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NMOS Transistor: Saturation Region If v DS increments above triode locale confine, channel district vanishes, additionally said to be squeezed off. Current immerses at steady esteem, free of v DS. Immersion locale operation for the most part utilized for simple intensification. Microelectronic Circuit Design McGraw-Hill Chap1-14

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NMOS Transistor: Saturation Region (contd.) for is likewise canceled immersion or squeeze voltage Microelectronic Circuit Design McGraw-Hill Chap1-15

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Transconductance of a MOS Device Transconductance relates the adjustment in deplete current to an adjustment in door source voltage Taking subordinate of the expression for the deplete current in immersion locale, Microelectronic Circuit Design McGraw-Hill Chap1-16

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Channel-Length Modulation As v DS increments above v DSAT , length of drained divert past squeeze off point, D L, increments and real L diminishes. i D increments somewhat with v DS as opposed to being consistent. l = channel length regulation parameter Microelectronic Circuit Design McGraw-Hill Chap1-17

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Depletion-Mode MOSFETS NMOS transistors with Ion implantation handle used to shape an implicit n - sort divert in gadget to interface source and deplete by a resistive channel Non-zero deplete current for v GS =0, negative v GS required to turn gadget off. Microelectronic Circuit Design McGraw-Hill Chap1-18

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Transfer Characteristics of MOSFETS Plots deplete current versus entryway source voltage for a settled deplete source voltage Microelectronic Circuit Design McGraw-Hill Chap1-19

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Body Effect or Substrate Sensitivity Non-zero v SB changes edge voltage, bringing on substrate affectability demonstrated by where V TO = zero substrate predisposition for V TN (V) g= body-impact parameter ( ) 2F F = surface potential parameter (V) Microelectronic Circuit Design McGraw-Hill Chap1-20

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Enhancement-Mode PMOS Transistors: Structure P - sort source and deplete areas in n - sort substrate. v GS <0 required to make p-sort reversal layer in channel locale For current stream, v GS< v TP To keep up switch predisposition on source-substrate and deplete substrate intersections, v SB <0 and v DB <0 Positive mass source potential causes V TP to end up more negative Microelectronic Circuit Design McGraw-Hill Chap1-21

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Enhancement-Mode PMOS Transistors: Output Characteristics For , transistor is off. For more negative v GS , deplete current increments in greatness. PMOS is in triode area for little estimations of V DS and in immersion for bigger qualities. Microelectronic Circuit Design McGraw-Hill Chap1-22

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MOSFET Circuit Symbols (g) and(i) are the most generally utilized images as a part of VLSI rationale plan. MOS gadgets are symmetric. In NMOS, n + locale at higher voltage is the deplete. In PMOS p + district at lower voltage is the deplete Microelectronic Circuit Design McGraw-Hill Chap1-23

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Process-characterizing Factors Minimum Feature Size , F : Width of littlest line or space that can be dependably exchanged to wafer surface utilizing given era of lithographic assembling apparatuses Alignment Tolerance, T: Maximum misalignment that can happen between two cover levels amid manufacture Microelectronic Circuit Design McGraw-Hill Chap1-24

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Mask Sequence for a Polysilicon-Gate Transistor Mask 1: Defines dynamic range or thin oxide area of transistor Mask 2: Defines polysilicon door of transistor, adjusts to veil 1 Mask 3: Delineates the contact window, alogns to veil 2. Veil 4: Delineates the metal example, adjusts to cover 3. Channel locale of transistor shaped by crossing point of initial two cover layers. Source and Drain locales shaped wherever veil 1 is not secured by cover 2 Microelectronic Circuit Design McGraw-Hill Chap1-25

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Basic Ground Rules for Layout F=2λ T=F/2= L, L could be 1, 0.5, 0.25 m, and so forth. Microelectronic Circuit Design McGraw-Hill Chap1-26

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Internal Capacitances in Electronic Devices Limit high-recurrence execution of the electronic gadget they are connected with. Confine exchanging velocity of circuits in rationale applications Limit recurrence at which helpful intensification can be acquired in speakers. MOSFET capacitances rely on upon operation district and are non-straight elements of voltages at gadget terminals. Microelectronic Circuit Design McGraw-Hill Chap1-27

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NMOS Transistor Capacitances: Triode Region C bull " =Gate-channel capacitance per unit area(F/m 2 ). C GC =Total entryway channel capacitance. C GS = Gate-source capacitance. C GD =Gate-deplete capacitance. C GSO and C GDO = cover capacitances (F/m). Microelectronic Circuit Design McGraw-Hill Chap1-28

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NMOS Transistor Capacitances: Triode Region (contd.) C SB = Source-mass capacitance. C DB = Drain-mass capacitance. A S and A D = Junction base zone capacitance of the source and deplete locales. P S and P D = Perimeter of the source and deplete intersection districts. Microelectronic Circuit Design McGraw-Hill Chap1-29

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NMOS Transistor Capacitances: Saturation Region Drain no longer associated with channel Microelectronic Circuit Design McGraw-Hill Chap1-30

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NMOS Transistor Capacitances: Cutoff Region Conducting channel district totally gone. C GB = Gate-mass capacitance C GBO = entryway mass capacitance per unit width. Microelectronic Circuit Design McGraw-Hill Chap1-31

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SPICE Model for NMOS Transistor Typical default values utilized by SPICE: K n or K p = 20 m A/V 2 g = 0 l = 0 V TO = 1 V m n or m p = 600 cm 2/V.s 2 F = 0.6 V C GDO = C GSO =C GBO =C JSW