PanSTARRS Gigapixel Camera System

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PanSTARRS Gigapixel Camera System John Tonry (IFA), Gerard Luppino (IFA), Peter Onaka (IFA), Barry Burke (MITLL) Scope of Gigapixel Camera exertion. WIYN telescope cooperation. OTA advancement status OTA test arrange OTA bundle, central plane and cryostat outline. OTA controller gadgets outline and advancement. Plot

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Scope of Gigapixel Camera Effort Part of Detector/Camera System Scope?

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WIYN Telescope Collaboration Non Binding Collaboration WIYN Developing One-Degree Imager (ODI) Camera System Nearly Identical to one of the PanSTARRS Gigapixel Cameras.

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Outline Overview of OTA Principal plan and process challenges Pixel format Logic outline, creation, and late results Metallization and interconnects Other OTA outline issues and alternatives Die size and cushions Enhanced substrate E fields Compatibility of plan with CMOS choice Mini-OTA (MOTA) choices Process choices and parcel 1 parts Design status and rundown

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Orthogonal Transfer Array (OTA) OTCCD cells 8  8 exhibit of little OTCCDs , each ~500  500 pixels* OTCCD cells freely timed through on-chip control rationale Cells read out one line at once at 1-MHz read rate; readout time ~ 2 s Subset of cells (ordinarily five) selectable for following guidestars at ~30-Hz rates * (12 um: 480 x 496; holes 9 x 28, 10 um: 574 x 594; holes 11 x 35)

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Detector Details – Overview Each CCD cell of a 4K  4K OTA Independent ~500  500-pixel CCDs Individual or aggregate tending to 1 arcmin field of view Dead cells extracted, yield >50% Bad segments restricted to Cells with brilliant stars for directing 8 yield channels for each OTA Fast readout (8 amps, 2 sec) Disadvantage – 0.1 mm holes, yet crevices and dead cells are dithered out at any rate 5 cm

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Outline Overview of OTA Principal plan and process challenges Pixel format Logic plan, manufacture, and late results Metallization and interconnects Other OTA outline issues and choices Die size and cushions Enhanced substrate E fields Compatibility of outline with CMOS choice Mini-OTA (MOTA) choices Process choices and parcel 1 parts Design status and synopsis

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Principal Challenges OTCCD yield was low as of not long ago (part 4) Pixel design gives off an impression of being basic to high return Control rationale Except for some preparatory test structures nMOS has not been a piece of Lincoln CCD handle Design and recreation expectation to absorb information Metallization Extensive utilization of two levels of metal New planarized metal process as of late created on different projects; test-structure information are empowering

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OTCCD Process Issues Polysilicon stackup must be minimized High anxieties might be an element Metallization prepare requires low entryway profile (see consequent diagram) OTCCD part 4 had high return after pixel re-outline Design rules Max of two poly layers over channel stops Max of three poly layers over channel districts

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Poly Pileup Areas of three-and four-poly stacks Three-poly stacks just Revised pixel design Original pixel format

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OTCCD Types Type 1 OTCCD Most involvement with this style: 2K  4K, 1024  1320, 512  512 (every one of the 15-µm pixels) 2K  4K now has great yield (CCID-28, parcel 4) Type 2 Higher symmetry however no undeniable manufacture advantage Only 512  512 (15-µm pixels) made up to this point

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Poly stackup Minimum poly linewidth Well limit OTA Pixel Designs Experience to date is with 15-µm pixels Desired pixel sizes are ≤ 12 µm 12-µm pixel: generally safe 10 µm: direct hazard 8 µm: high hazard Tight exchange space: Poly1, poly2 design Channel stops Poly3, poly4 format Example of 10-µm pixel plan

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Pixel Design Choices Current arrangement: four adaptations of OTA, each with various pixel format Two 12-µm-pixel plans as least hazard OTA-a: sort 1 OTA-b: sort 2 Two 10-µm pixel outlines, both scaled from 12-µm formats, as to some degree higher hazard yet nearer to fancied pixel measure OTA-c: sort 1 (scaled OTA-a pixel) OTA-d: sort 2 (scaled OTA-b pixel) Pixel a Pixel b

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Logic Design Considerations Requirements Cells must be autonomously addressable Parallel timekeepers for every phone can be set to one of three states Active (picture readout, redesign pixel shifts, and so forth.) Standby (picture securing between overhauls) Floating (shorted stages) Cell yields read out one line at once Maximum of one cell/section read whenever Desired Low FET check, conservative design Low power Compatible with parallel move rate > 100 kHz

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Control Logic Overview NMOS rationale picked Easy to add to n-channel CCD process(+) Power wasteful (- ) Early begin on improvement Oct 2002: SPICE parameter extraction from test MOSFETs on CCID-28, parcel 4 February 2003: preparatory OTA rationale outlines added to SST cover set June 2003: rationale plans on SST wafers in test!

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Addressing and Control Logic: Current Design Data are hooked at every phone until tended to again Flexible operation Cell can be timed with video on or off Standby mode amid science picture securing Defective parallel entryways can coast

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Final Control Logic Design 39 FETs, 0.6–0.8 mW control scattering Operation with V DD =5.0 V; acknowledges contributions with 5-V CMOS-good levels Further variations under study for incorporation as test structures

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Logic Designs on SST Wafers Designs Simple building-square circuits Preliminary OTA tending to and control rationale (since changed) Advanced forceful plans Important approval of outline and reproduction strategies Original OTA rationale outline (61 FETs) Closeup of circuit

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Q First Test Circuit Results Latch circuit works for V DD = 5.0 V Two forms (distinctive plan rules) effective Threshold voltages fairly higher than anticipated Fix is straightforward embed measurement modification D Q CLK D CLK

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Additional NMOS Test Results First form of OTA control rationale works! Plan from January; utilizes 61 FETs Functions with V DD =5 V

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Metallization OTA utilizes substantial measure of wiring Two levels of metal (light and dull blue) Design rules kept intentionally casual Line widths and spacings  5 µm

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Metallization Process: Planarized Dielectrics with W Plugs Same approach as utilized as a part of current CMOS forms Process diagram: Thick oxide stored and planarized (CMP) Contact gaps scratched, loaded with W (damascene process) Metal straps Repeat for second metal Advantages W fittings can be smaller and more profound than traditional contacts for AlSi Planar surface better for fine lithography Shorts yield from test wafers is high Poly stackups must be minimized to keep up poly/metal detachment Cross area from CCID-34 test wafer

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Metal Strapping Experiments Used existing extensive imager (~20 cm 2 ) cover set and included metal straps over chanstops Critical test (entryway shorts initiated by straps) demonstrated high return Significant contrasts from standard LL CCD handle Dry-carved metal (versus wet) Ti/TiN/AlSi (versus AlSi) W plugs (new) Metal straps

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Metallization Options Placing computerized related lines over pixel clusters builds fill figure by 3.3% Is this an advantageous pick up? Handle suggestions Greater shot of metal/poly shorts More space for metal lines: less metal/metal shorts Metal lines can be more extensive: speedier timing, less defenseless against line breaks Metal-over-pixels choice requires three veil changes

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Outline Overview of OTA Principal outline and process challenges Pixel format Logic plan, creation, and late results Metallization and interconnects Other OTA plan issues and alternatives Die size and cushions Enhanced substrate E fields Compatibility of outline with CMOS choice Mini-OTA (MOTA) choices Process choices and parcel 1 parts Design status and synopsis

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Die Size Exclusion zone > 5 mm picked  kick the bucket estimate = 49.5  4 9.5 mm Compatible with STA/Dalsa necessities Saw kerf ≈ 70 µm  sawn pass on size = 49.43  49.43 mm

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Pad Layout Mirror symmetric cushion format: FI and BI gadgets utilize same bundle and I/O Center Right side Left side

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Deep Depletion with Substrate Bias Chanstop and base substrate electrically associated: base substrate can't be one-sided Chanstop and base substrate electrically secluded: base substrate can be one-sided

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Advantages of Deep Depletion V sub V sub Front-lit up – Improved high-vitality x-beam reaction Back lit up – Increased vertical E fields  more tightly PSF

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Measured Depletion Depths Deep-exhaustion CCD (CCID-42) 512  512, 15-µm-pixel outline exchange gadget Same pinouts as all past 512 2 gadgets Data taken from capacitance-voltage test structure that speaks to CCD design Depletion profundities > 150 µm effectively accomplished

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X-beam Data from MIT/CSR Si assimilation length at 22 keV=1370 µm QE  consumption profundity Improved discovery of top notch occasions ~2  check increment predictable with ~2  increment in exhaustion profundity

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Deep Depletion Current arranges Thin four CCID-42 chips to differing thicknesses (60 – 150 µm) Measure QE and PSF versus thickness and substrate inclination (information pertinent to Pan-STARRS) Devices prepared for test in 2 – 3 months Backside treatment: II/LA or chemisorption charging? OTA outline can incorporate profound consumption choice

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Why OTA/CMOS Hybrid? Favorable circumstances Risk diminishment if solid OTA falls flat Simplifies OTCCD handling (no NMOS, extensive system of metal lines) Pathfinder for additional on-sensor preparing in CMOS Possible change in fill calculate Disadvantages Additional costs: CMOS outline, fab & test, knock holding Adjustments to diminishing procedure

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Hybrid OTA chip CMOS control chip Bump holding Hybrid OTA/CMOS sensor

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OTA Design for CMOS Hybrid Optional metal veil conveys all OTA cell capacities to cushions for knocking Can be done as process split (one cover change, two veil steps erased) Fill consider unverifiable; superior to gauge yet mama