On Design-Manufacturing Integration Talk at Intel June 25, 2003 Andrew B. Kahng, UCSD CSE ECE Departments email: abku

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Layout. The Problem, Scope and GoalsExample: Cost-Driven RETExample: Intelligent MDPExample: Analog Rules, Restricted Layout,

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On Design-Manufacturing Integration Talk at Intel June 25, 2003 Andrew B. Kahng, UCSD CSE & ECE Departments email: abk@ucsd.edu URL: http://vlsicad.ucsd.edu

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Outline The Problem, Scope and Goals Example: Cost-Driven RET Example: Intelligent MDP Example: Analog Rules, Restricted Layout, … Conclusions

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The Problem Steadily expanding plan exertion, turnaround time, and venture hazard Example side effects (next slides): definite directing "Dull Future" (12 th Japan DA Show talk, 2000) Cost and consistency disappointments  Electronics industry makes workarounds stages  programmability  programming  Semiconductor industry slows down  No retooling cycle for provider enterprises (e.g., EDA) Cf. Intel declaration re 157nm lithography

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Reticle Enhancement (versus Steering) 193nm, 157nm are late   , span of impact >> F Pattern setting progressively predominant Iso versus thick, microloading/halation, … RETs = handles: opening, stage, light, setting Affect attainability of cover compose, check  Complexity incline: display based RETs, AIM devices on top of it, test structure-based RLCX adjustment, and so forth

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Routing Rules (1) Minimum zone rules and by means of Stacking vias through various layers can bring about least region infringement (arrangement resistances, and so forth.) Via cells can be made that have more metal than least by means of cover (utilized for middle of the road layers in stacked vias) Multiple-cut vias Use numerous slice vias cells to expand yield and unwavering quality Can be required for wires of specific widths Multiple by means of cut examples have diverse dispersing rules Four cuts in quadrilateral; five cuts in cross; six cuts in 2x3 exhibit; … With wide-wire dividing rules, confounds stick get to Cut-to-write separating rules  check both slice to-slice and metal-to-metal while considering by means of to-by means of dividing Line-end augmentations Vias or line closes require extra metal cover (0 th - arrange OPC)

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Routing Rules (2) Width-and Length-subordinate dispersing rules Width-subordinate standards: domino impacts Variant: "parallel run" (longer parallel runs  all the more separating) Measuring length and width: radiance rules influence calculation Influence guidelines or stub leads A fat wire, e.g., control/ground net, will impact the separating principle inside its surroundings  any wire that is X um far from the fat wire should be in any event Y um far from whatever other geometry. Illustration: fat wire with thin tributaries greater dispersing around each wire inside certain separation of the thin tributaries ECO inclusion of a tributary causes inconveniences Strange runs and spreading when wires enter an affected territory

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Example: LEF/DEF 5.5, April 2003

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Example: LEF/DEF 5.5, April 2003

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Routing Rules (3) Density Grounded metal fills (sham fill*) Via isodensity rules and by means of homestead standards (through layers must be filled and opened, have width-subordinate dividing guideline analogs, and so forth.) Non-rectilinear (  - geometry) directing X-Architecture: http://www.xinitiative.org/Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/, LSI Logic licenses Landing cushion shapes (isothetic rectangle versus octagon versus circle), diverse spacings (~1.1x) amongst slanting and Manhattan wires, and so on. More exemptions More non-default classes (timing, EM dependability, … ) Not simply power and clock >0.25um width might be "wide"  numerous special cases

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Routing Rules Degrade consummation rates, runtime effectiveness "Postprocessing" likely no longer suffices E.g., radio wires Can (ought to) (must) switches "locally" address these issues?

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Other Symptoms: NRE Cost Runtimes for cover information prep (MDP), veil compose, cover examination NRE cost  runtimes  shapes many-sided quality Context-subordinate breaking P. Buck, Dupont Photomasks, July 2001

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Other Symptoms: BEOL Yield More than half of calamitous yield misfortune is in BEOL Copper is stored  can induce yield misfortune instruments Open issues (3x more pervasive than short or spanning issues) High-resistance by means of deficiencies Cf. "non-tree directing" for unwavering quality and yield? Gigantic measure of changeability spending plan is in planarization Copper is delicate  double material clean systems Oxide disintegration and copper dishing  cross-sectional fluctuation, between layer spanning flaws, … Much, significantly more… Low-k dielectrics: warm properties, anisotropy, nonuniformity Resistivity at little conduit measurements (grain and obstruction layer impacts)

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Density Management and Futures Physical model based thickness guidelines and fill combination Current "coevolved" state: Wrong principles, feeble instruments W. Grobman, Motorola, DAC-2001

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Evolutionary Paths Conflicting objectives Designer: "flexibility", "reuse", "relocation" EDA: "support mode" Process/foundry: "upgrade saw esteem" (= include rules)  Prisoner's Dilemma Fiddling: Incremental, straight extrapolation of current direction "GDS-3" Thin post-handling layers (decompaction, RET addition, … )

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DAC-2003 Nanometer Futures Panel: Where ought to additional R&D $ be spent?

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Co-Evolutionary Paths Designer, EDA, and prepare groups participate and co-develop to keep up the cost (esteem) direction of Moore's Law Must escape Prisoner's Dilemma Must be monetarily practical At 90nm to 65nm move, this involves survival for the overall semiconductor industry Example Focus Areas: Manufacturability and cost/esteem enhancement Restricted format Intelligent veil information prep Analog guidelines (Layout and plan advancements) Disclaimer: Not an entire posting

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Basic Goals Bidirectional outline producing information pipe Fundamental drivers: cost, esteem Pass utilitarian goal to cover stream Example: RET for unsurprising circuit execution, work RETs ought to win $$$, lessen execution variety  cost-driven, parametric yield compelled RET Pass breaking points of cover stream up to outline Example: maintain a strategic distance from amendments that can't be made or confirmed N.B.: 1998-2003 papers/instructional exercises: http://vlsicad.ucsd.edu/~abk/TALKS/

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Outline The Problem, Scope and Goals Example: Cost-Driven RET Example: Intelligent MDP Example: Analog Rules, Restricted Layout, … Conclusions

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Design for Value * Mask cost incline  Design for Value (DFV) Design for Value Problem: Given Performance measure f Value work v(f) Selling guides f i comparing toward different estimations of f Yield work y(f) Maximize Total Design Value =  i y(f i )*v(f i ) [or, Minimize Total Cost] Probabilistic improvement administration * See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", IEEE ASIC/SoC Conference , September 2002, pp. 411-415.

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Obvious Step: Function-Aware OPC Annotate highlights with "required sum" of OPC E.g., why remedy sham fill? Controlled by plan properties, for example, setup and hold timing slacks, parametric yield criticality of gadgets and elements Reduce add up to OPC embedded (e.g., SRAF use) Decreased physical check runtime, information volume Decreased veil cost coming about because of less elements Supported in information positions (OASIS, IBM GL-I) Design through cover instruments need to make, utilize comments

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Cost-Driven RET MinCorr (DAC-2003): Different levels of RET = diverse levels of CD control OPC arrangements because of K. Wampler, MaskTools, March 2003 CD concentrates because of D. Pramanik, Numerical Technologies, December 2002

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Performance Measure = Delay Selling point delay = circuit defer which accomplishes craved level (say 99%) of parametric yield Goal: Achieve offering point delay with least cost of RET's (OPC)

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MinCorr: The Cost of Correction DFV Problem Given : Admissible levels of rectification for every design include and the comparing postpone affect (mean and fluctuation) Find : Level of amendment for every format highlight to such an extent that a recommended offering point deferral is achieved Objective : Minimize add up to cost of revisions

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Gate postpone A C Arrival time B Arrival time Propagate landing time appropriation Statistical Timing Analysis Statistical STA (SSTA) gives PDFs of entry times at all hubs

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Variation Aware Library Model Capacitance and defer values supplanted by ( ,) match Sample variety mindful .lib pin(A) { course : input; capacitance : (0.002361,0.0003); } … timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 ("0.028, 0.044, 0.076"); index_2 ("0.00158, 0.004108, 0.00948"); values ( \ "(0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)", … .

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Generic Cost of Correction Methodology Nominally Correct SP&R Netlist Min. Amended Library Statistical STA (SSTA) gives PDFs of landing times at all hubs Assume variety mindful library models (for postponement) are accessible SSTA Yield Target met ? Y EXIT N All Correction Libraries Correction Algorithm All Correction Libraries SSTA

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Generic Cost of Correction Methodology Nominally Correct SP&R Netlist Min. Adjusted Library Statistical STA (SSTA) gives PDFs of landing times at all hubs Assume variety mindful library models (for deferral) are accessible Statistical STA presently has runtime and adaptability issues SSTA Yield Target met ? Y EXIT N All Correction Libraries Correction Algorithm All Correction Libraries SSTA

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MinCorr: Parallels to Gate Sizing Assume Gaussian-ness of conveyances wins  + 3 compares to 99% yield Perfect relationship of variety along all ways Die-to-Die variety  1+2 + 3 1+2 =  1 + 3 1 +  2 + 3 2 Resulting linearity permits proliferation of (  +3  ) or 99% (offering point) deferral to essential yields u

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