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WHO WE ARE Non-benefit Microelectronics dealer, committed to provide:Low expense building tests of IC outlines, Low-volume creation administration, ~50% of MOSIS\' submicron runs are

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WHO WE ARE Non-benefit Microelectronics agent, devoted to give: Low cost building tests of IC plans, Low-volume generation benefit , ~50% of MOSIS' submicron runs are "Committed runs" (i.e., low volume creation runs) Access to most recent generation demonstrated advancements Single purpose of interface to its clients for extra administrations or items offered by accomplice sellers, Latest adaptation of foundries' outline/electrical standards and flavor models Educational Program for Microelectronics Design Experience - 22 Years of Operation Unique: Only non-supported administration on the planet which gives access to various advances & fabricators

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TYPES OF CUSTOMERS Companies With Pilot Projects Requiring Engineering Samples for Proof of Concept Companies With Small Volume Production Requirements Government Agencies Universities : Research, Education (VLSI Design Classes)

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WHAT WE DO Provide Access to different advances and fabricators Organize Multiproject and Single Customer Dedicated Runs Collect and Merge Designs Provide Fully Checked Merged Designs to Mask Shop Production Compatible Masks to Foundry Mid Range Volumes (e.g. 500, 2000) Available Support Users Design Kit Distribution Handle Design Questions Design Rules, Modeling, IP, Etc. Incorporate Reference Designs on MPW Runs (To check yield) Work Closely With Design, IP Providers

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Sample Multiproject Wafer

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Sample Multiproject 0.18  Reticle

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Sample Multiproject 0.18 µ Reticle

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THREE PHASES: Phase I: 1981-1985 – 100% DARPA Direct Funding Phase II: 1985-1994 - Multi-Agency Direct Funding DARPA: ~67% ==>80% Subsidized All Undersubscribed Runs NSA ~26% ==> 10% NSF/DARPA Educational Program Starts : ~$900k/yr. NSF : ~7% ==> 5% Commercial Customers : ~0%  5% Helped to settle Government Costs by utilizing overabundance zone . Stage III: 1994-2003 - Self-Sustaining Operations Commercial Customers are Only Source of Revenue Multi-Sponsor Ed. Program NSF (1994-1998) Commercial Firms MOSIS SRC/SIA (2000-2002)

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IBM 5HP/DM: SiGe 0.50µ IBM 6HP/6DM: SiGe 0.25µ IBM 6RF: CMOS 0.25 µ IBM 7SF: CMOS 0.18  IBM 7WL CMOS 0.18  IBM 8SF: CMOS 0.13  AMI ABN: CMOS 1.50µ AMI C5N: CMOS 0.50µ AMI C3N CMOS 0.35µ TSMC CL035: 0.35µ TSMC CL025/CM025: 0.25µ TSMC CL018/CM018: 0.18µ Peregrine SOI-SOS: 0.50µ AMS BiCMOS (CMP) 0.8 µ OMMIC GaAs (CMP) 0.2 µ VITESSE InP HBT Available Technologies

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SIA 2001 Roadmap +MOSIS Roadmap

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Gate Delay (Ps) versus Include Size 31 Stage CMOS Ring Oscillator

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FAB COSTS Lithography has turned into the most critical cost thing in profound submicron fab Wafer and veil costs generally the same until the 0.35 µ hub Different lithography advancements 1X Stepper Lithography Medium payload: ~ 900 sqmm; 1.5 µ is least useful utmost 5X Stepper Lithography Small Payload: 480 sqmm max. Innovation of decision for 1.2 µ and underneath 0.5 µ - 1.6 µ veil tech. Direct 0.18 µ - Mix and Match: 5X and 4X Stepper/Scanner Reticles VERY EXPENSIVE 25x cost of 1.5 µ covers 0.13 µ-Mix and Match: 5 and 4x US $500k-$750k per veil set

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Optical Lithography: Resolution Limits

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RESOLUTION ENHANCEMENTS: OPTICAL PROXIMITY CORRECTIONS Hammerhead Jogs Inside serifs (clear) Outside serifs (chrome)

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RESOLUTION ENHANCEMENTS: OPC For Contacts Optical Proximity Correction No OPC Applied Diffraction at corners of little vias or potentially contacts brings about deficient oppose introduction. Not required for 0.35um or bigger Is required for S < 0.2 um CONTACT ON WAFER: 0.5 X 0.5um CONTACT ON MASK : 2.5 X 2.5um CORNER BOX DIMENSIONS: 0.5um x 0.5um

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RESOLUTION ENHANCEMENTS: PHASE SHIFT MASKS PHASE SHIFT Masks extremely costly Geometry subordinate Difficult to get subjective shapes Incoming radiation Chrome Pattern Groove Depth = 1/2 wavelength of light Interference impacts between light going through the score and the center of the element, create a sharp line.

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DEEP SUBMICRON PLANARIZATION Passivation Layer Metal Lines If metal lines are near one another, passivation layer can be planarized to the required degree, generally, extra metal lines must be added to the outline's photograph covers. This procedure ought to be straightforward to the originator.

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EDUCATIONAL PROGRAM Description The MEP gives free creation of incorporated circuits planned by understudies at certify instructive organizations in the U.S., Central and South America, Spain, New Zealand and Australia Geographical points of confinement set by accessible MOSIS assets Two sorts of records INSTRUCTIONAL RESEARCH Eligibility Fabrication of understudy outlines is accessible to authorize colleges who consent to the accompanying terms: Design, recreation, and testing devices must be determined A report must be sent to MOSIS for each manufactured circuit . Additionally Details can be found at h ttp://

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ACCOUNT DESCRIPTIONS INSTRUCTIONAL Program Designs from understudies in composed classes – Undergraduate and Graduate Enrollment at start of the Quarter/Semester Each understudy is dispensed a "Modest Chip Unit" of range Detailed reports on chip test results are required for each chip created "The chip filled in not surprisingly" is not an adequate report Technologies CMOS Analog/computerized 1.5µ, 0.5µ 1.5µ Technology: Tiny Chip Unit size is 2.2mm X 2.2mm 0.5µ Technology: Tiny Chip Unit size is 1.5mm X 1.5mm

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ACCOUNT DESCRIPTIONS RESEARCH Program Restricted to non-supported research : Thesis or research ventures Mini-proposition (2-3 pg., or increasingly if fundamental) required: Design depiction, outline apparatuses, testing, recreation, reason. One outline for each proposition: Must be clear and point by point, including wanted innovation and an exact chip measure gauge . Last report required upon finish May be a duplicate of an inner report or a distributed paper Projects are chosen by MOSIS in light of legitimacy and creativity Selected plans are manufactured in frequently booked MOSIS runs, on a space accessible premise . Innovations CMOS 1.5 µ, 0.5µ, 0.35 µ , 0.25 µ , 0.18 µ, 0.13µ; SiGe: 0.5 µ & 0.25µ

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Program Oversight and Institution Eligibility Program Oversight MOSIS Advisory Council for Education University Professors, SRC, Industrial Contributors Institution Eligibility All U.S. Colleges Non-U.S. Colleges: Funding Provided Solely by MOSIS 1999: Instructional and Research MEP reached out to incorporate Latin American, New Zealand and Australian Universities 2002: Research MEP Access stretched out to incorporate Europe Current topographical confinements are set by accessible MOSIS assets.

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Educational Program Funding 1984-1994: Funding was given exclusively by: National Science Foundation (NSF) (~$575k/yr) Defense Advanced Projects Agency (DARPA) (~$375k/yr) 1995-1999: Funding gave by: National Science Foundation (NSF) AMI, HP: Wafer run gifts MOSIS: Administrative costs 2000-2003 AMI: Wafer run gifts: 1.5um & 0.5um (4-5runs/yr) IBM: Wafer fab 0.5um & 0.25um SiGe SIA/SRC: Instructional &Advanced Program Fab (~$335k/yr) Dupont: Discounted photomasks for instructive just runs. MOSIS Provides: All authoritative costs (~$110k/yr) Instructional and propelled Program Fab (~$600k/yr)

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SUMMARY Low Cost Prototyping Regularly Scheduled Prototype Runs Low Volume Production Access to Latest TSMC and IBM Production Technology Access to Important Third Party Resources Monitors Quality of Vendors and Processes Privately Funded VLSI Educational Program

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MEP PERFORMANCE and Technologies Ten Years: 1990 through 1999 comprehensive 12,130 Student Designs Processed > 50,000 Students Participated Total of 195 U.S. Colleges 1984-2003: Technologies Offered 1984-1987: NMOS (3-4  ), CMOS (2-3  ) 1988-1997: CMOS (2  ) 1997-1999: CMOS (2, 1.5, 0.5, 0.35, 0.25  ) 1999-2000: CMOS(1.5, 0.5, 0.35, 0.25  ); SiGe ; 2001-> : CMOS(1.5, 0.5, 0.35, 0.25, 0.18  ); SiGe; SOS

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MOSIS Web Forms Project accommodation, following, and so on. Secure or non-secure

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COMPATIBLE DESIGN LIBRARIES Artisan Commercial Firms Free Digital Libraries, I/Os & Memories TSMC 0.25µ and 0.18µ procedures Work with Commercial EDA instruments: Avant!, Cadence, Synopsis Universities Complete front end perspectives of center & I/O cells Behavioral, combination, reenactment, P&R No GDS, MOSIS Instantiates the cells

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COMPATIBLE DESIGN LIBRARIES Barcelona Design Tools & administrations for simple amalgamation of A/Ds, D/As, Op-Amps, PLLs AMI 0.5µ, TSMC 0.35µ, 0.25µ, & 0.18µ Processes LEDA Systems Analog & RF Cells for the TSMC 0.25µ, & 0.18µ Processes Nurlogic Digital, Analog/RF & Special I/O Cells for: TSMC 0.25µ, & 0.18µ Processes IBM 6HP SiGe 0.25µ

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Standard Data Preparation Project Check Checks outline