Intrude on taking care of and utilizing inner clock

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Slide 1

Equipment/programming Interfacing

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Interrupt taking care of and utilizing inner clock Two path for processor to acknowledge outside information: Waiting for information: Processor will end and listening to the info port until information is transmitted while(data is not updated){ read information from address of some I/O port }

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Interrupt taking care of and utilizing inside clock Interrupt: Data entry will begin an intrude on demand to processor, when a hinder is produced, processor will stop it's present work and swing to interfere with administration work (information get), and continue work after hinder is taken care of. interrupt_func() { transmit information from I/O port to processor } Main() { setup intrude on taking care of capacity }

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Interrupt Request "interfere with demand " (or IRQ ) is utilized to allude to either the demonstration of intruding on the transport lines used to flag an intrude, or the intrude on information lines on a Programmable Interrupt Controller Generated when an I/O occasion happens, took care of by interfere with controller Interrupts from various sources are separated by IRQ line number

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IRQ setting in DE2 Computer

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Interrupt handler work NIOS Processer keeps an extraordinary address in memory advertisement the section point for intrude on handler work Exception Vector: stores the address of intrude on handler work, when an IRQ is gotten by processor, it will spare the guideline connection and bounce to intrude on handler work.

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How to utilize interfere with handler Enable relating IRQ line to processor in SOPC manufacturer Set I/O gadgets to empower outer intrude on era Enable the interruptmask enroll of Parallel I/O The ITO bit in inner clock control enlist Write intrude on handler work Register interfere with handler work

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Code test for intrude on handler setup Include records: #include "system.h" #include "alt_types.h" #include "sys/alt_irq.h" #include "sys/alt_sys_init.h"

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Pseudo-Code test for intrude on handler setup void interrupt_handler() { … } primary() { empower framework irq enlist handler of irqX as interrupt_handler }

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Internal Timer NIOS Internal Timer Works as a stop watch, period enlist and control signs are set by client by programming, once began, counter will include down from the esteem time frame enlist to 0 and produce a hinder when time is over.

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Top-level clock outline

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Timer design

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Timer arrangement Configured in SOPC Builder

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Register File for Internal Timer

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Register File for Internal Timer

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Register File for Internal Timer

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Register File for Internal Timer

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How to utilize inner clock in programming Internal clock will loopingly include down from esteem period enlist to 0, when counter achieves 0, a hinder on IRQ 1 will be created, client need to compose IRS work for IRQ 1 to catch clock occasions In DE2 Computer, the time of clock is 1 ms, implies the hinder will happen 1000 every second

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How to utilize inward clock in programming #include "system.h" #include "alt_types.h" #include "altera_avalon_timer_regs.h" #include "altera_avalon_timer.h" #include "sys/alt_irq.h" #include "sys/alt_sys_init.h"

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Macros for clock enroll record get to IORD_ALTERA_AVALON_TIMER_STATUS(base) IOWR_ALTERA_AVALON_TIMER_STATUS(base, information)/Read/keep in touch with 16 bits status enlist IORD_ALTERA_AVALON_TIMER_CONTROL(base) IOWR_ALTERA_AVALON_TIMER_CONTROL(base, information)/Read/keep in touch with 16 bits control enlist IORD_ALTERA_AVALON_TIMER_PERIODL(base) IOWR_ALTERA_AVALON_TIMER_PERIODL(base, information)/Read/keep in touch with lower 16 bits of period enlist IORD_ALTERA_AVALON_TIMER_PERIODH(base) IOWR_ALTERA_AVALON_TIMER_PERIODH(base, information)/Read/compose to higher 16 bits of period enlist

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How to utilize inside clock in programming Write client IRS work static void Timer_Interrupts(void *context,alt_u32 id) { if(Timer_counter >= 1000)/* 1S */{ Timer_counter = 0;/worldwide variable to store achieved counter occasion <USER CODE HERE> } else { Timer_counter++; } IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_BASE, 0x00);//clear status enlist }

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How to utilize interior clock in programming Register IRS alt_irq_register(TIMER_IRQ,NULL,Timer_Interrupts);/Register IRS IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_BASE, 0x07);/Start clock

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How to catch Timer occasion in client program Keep a worldwide variable for putting away data from clock occasions, in principle work, check the worldwide variable to upgrade clock occasions static int timer_event; interrupt_handler() { … . /set timer_event } fundamental() { enlist IRS work while(timer_event redesigned) { … client activities }

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Summary DE2 Computer An essential equipment setup in Quartus for implanted framework programming outline Parallel I/O Basic, enroll record structure and programming 7-Segment LED Driven by parallel I/O, programming and show Interrupt taking care of Basic ideas, and how to use in programming Internal Timer Basic, enlist document structure and programming

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HW 1 Answer keys 1: Draw and portray the memory chain of command of an installed framework Figure 5-1

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2 Which memory part in a memory order is commonly situated on load up A: Level-2 reserve B: Main memory C: Secondary memory D: All of the above E: None of the above D

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[a] What is ROM [b] Name and depict three sort of ROM ROM=Read Only Memory, a kind of non-unstable memory that can be utilized to store information on an inserted framework for all time MASK ROM OTPROM EPROM ...

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[a] What is RAM [b] Name and depict 3 sorts of RAM Random Access Memory=location inside it can be gotten to specifically and arbitrarily SRAM SDRAM DRDRAM …

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[a] Draw cases of ROM, SRAM and DRAM memory cells [b] Describe the fundamental contrasts between these memory cells figure 5-6, figure 5-9, and figure 5-11 a ROM: contains bipolar or MOSFET transistor SRAM: 6 transistors, lost information when power off DRAM: one transistor and one capacitor, require invigorated to keep information

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SRAM is generally utilized as a part of outside reserve, on the grounds that SRAM is slower than DRAM FALSE

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What kind of memory is ordinarily utilized as primary memory DRAM

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[a] What is the distinction between level1,2,3 store [b] How would they all cooperate in a framework speed: quick, medium, moderate cost: high, medium, low Processor first check level 1 store, if miss, check level 2 store … if all stores miss, goes to principle memory

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[a] What is the most widely recognized plans used to store and recover information in reserve [b] what is the contrast between store hit and store miss Direct mapped, set acquainted, full affiliated Cache hit: the information is in the reserve miss: information is not in store

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Name and portray no less than 4 store swapping plans Optimal, LRU, FIFO, NRU

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Auxiliary memory is commonly arranged by information is gotten to True

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What is the contrasts between physical memory and coherent memory Physical memory is the genuine memory on board Logical memory is a virtual memory space, executed by OS, to give an advantageous approach to programming improvement

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17 (2) How can memory affect the execution of a framework Difference in band width and recurrence can back off information get to period Limited memory will as often as possible cause page blame, trading pages out from and into memory will be an extensive overhead for framework.

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