FPGA Design Flow

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1727 days ago, 2853 views
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Advanced Design Flow . Verilog Coding. Practical/Gate Simulation/Verification. Rationale Synthesis. Clock Tree InsertionFinal Layout. Last Design CheckDRC/LVS. Test-Insertion. Static Timing Analysis. Floorplanning/Place

Presentation Transcript

Slide 1

Verilog test seat Verilog demonstrate Verilog Netlist ngc standard piece FPGA Design Flow Verilog RTL Coding Tools Design Stage Verilog Design Text Editor Emacs, Nedit, Vi Functional/Gate recreation & Verification Modelsim SE Leda sdc Synthesis Xilinx ISE - XST Synplify Pro Logic Synthesis Pyhsical Design & Implementation Xilinx ISE Xilinx Impact ucf Physical Layout Device Configuration

Slide 2

Verilog test seat Verilog RTL Verilog Netlist Digital Design Flow Verilog Coding Design Stage Tools Verilog Design Text Editor Emacs, Nedit, Vi Functional/Gate Simulation/Verification Mentor - Modelsim SE Synopsys - Leda Synthesis Synposys - Design Compiler Logic Synthesis scr Test Insertion Synopsys - TetraMax Mentor - Fastscan Test-Insertion test.scr Static Timing Anal. Synopsys - Primetime Place & Route Cadence - Sensemble/SOC Encounter Synopsys - Apolllo Static Timing Analysis _pre.sdf techfile.lef techfile.gcf *.lef *.tlf *.def Floorplanning/Place & Route Clock Tree Insertion Cadence - CTgen Timing Extraction Synopsys - StarRXT Cadence - Pearl Clock Tree Insertion Final Layout ctgen.con DRC/ANT Checking Cadence - Assura, Dracula Mentor – Callibre _post.sdf Timing Extraction LVS Cadence - Assura, Dracula Mentor – Callibre Final Design Check DRC/LVS gds2

Slide 3

Analog Design Flow Schematic Entry Design Stage Tools Schematic Entry Composer Simulation Specter Layout Virtuosso Pyhsical Verification/Extraction Assura Caliber Layout techfile.lef techfile.gcf *.lef *.tlf *.def Post-Layout Simulation Specter Physical Verification/Extraction Post-Layout Simulation gds2

Slide 4

Verilog test seat Verilog RTL Verilog Netlist Mixed Signal Design Flow Cadence - SpectreVerilog Cadence - UltraSim Analog Flow Digital Flow Co-reenactment Environement Verilog Coding Behavioral Modeling Schematic Entry Functional/Gate Simulation/Verification Simulation Logic Synthesis scr Test-Insertion test.scr techfile.lef techfile.gcf *.lef *.tlf *.def Layout Static Timing Analysis _pre.sdf techfile.lef techfile.gcf *.lef *.tlf *.def Floorplanning/Place & Route Physical Verification/Extraction Clock Tree Insertion Final Layout ctgen.con _pst.sdf Timing Extraction Post-Layout Simulation gds2 Final Design Check DRC/LVS gds2

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