# EECS 40 Spring 2003

0
0
1093 days ago, 294 views
PowerPoint PPT Presentation

### Presentation Transcript

Slide 1

﻿Address 23 Computing Gate Delay 4/1/03 Prof. Andy Neureuther Discharging Capacitance through a MOS gadget? Identical resistance demonstrate for MOS CMOS Logic operation Path subordinate postpone Worst cae and Cascade EECS 40 Spring 2003

Slide 2

V DD p-sort MOS Transistor (PMOS) V IN-U Output I OUT n-sort MOS Transistor (NMOS) V OUT V IN-D Transient Gate Problem: Discharging and Charging Capacitance on the Output 5V => 0 V IN = V DD = 5V C OUT = 50 fF

Slide 3

V OUT (0) = 5V I OUT-SAT-D = 100 m A 100 I OUT-SAT-D = 100 m A C OUT = 50 fF 60 V IN = 5V I OUT ( m A) 20 0 3 5 V OUT (V) Output Propagation Delay High to Low When V IN goes High V OUT begins diminishes with time Assume that the essential voltage swing to bring about the following downstream entryway to start to switch is V DD/2 or 2.5V. That is the spread defer t HL for the yield to go from high to low is an ideal opportunity to go from V DD = 5V to V DD/2 =2.5V

Slide 4

V OUT (0) = 5V I OUT-SAT-D = 100 m A 100 I OUT-SAT-D = 100 m A C OUT = 50 fF 60 V IN = 5V I OUT ( m A) 20 0 3 5 V OUT (V) Output Propagation Delay High to Low (Cont.) When V OUT > V OUT-SAT-D the accessible current is I OUT-SAT-D For this circuit when V OUT > V OUT-SAT-D the accessible current is steady at I OUT-SAT-D and the capacitor releases. The proliferation postponement is in this way

Slide 5

R D Switched Equivalent Resistance Model The above model expect the gadget is a perfect steady current source. 1) This is not valid beneath V OUT-SAT-D and prompts to in correctnesses. 2) Combining perfect current sources in systems with arrangement and parallel associations is dangerous. Rather characterize a comparable resistance for the gadget by setting 0.69R D C equivalent to the D t found over This gives Each gadget can now be supplanted by this proportional resistor.

Slide 6

V OUT (0) = 5V I OUT-SAT-D = 100 m A 100 I OUT-SAT-D = 100 m A C OUT = 50 fF 60 V IN = 5V I OUT ( m A) 20 0 3 5 V OUT (V) ¾ V DD/I SAT Physical Interpretation ¾ V DD is the normal estimation of V OUT Approximate the NMOS gadget bend by a straight line from (0,0) to (I OUT-SAT-D , ¾ V DD ). Decipher the straight line as a resistor with 1/(slant) = R = ¾ V DD/I SAT

Slide 7

Switched Equivalent Resistance Values The resistor values rely on upon the properties of silicon, geometrical format, plan style and innovation hub. n-sort silicon has a transporter portability that is 2 to 3 times higher than p-sort. The resistance is conversely extent to the door width/length in the geometrical format. Plan styles may confine all NMOS and PMOS to be of a foreordained altered size. The current per unit width of the entryway increments about conversely with the linewidth. For comfort in EE 42 we accept R D = R U = 10 k W

Slide 8

V DD V DD R D V OUT V OUT V IN = Vdd V IN = Vdd C OUT = 50fF C OUT = 50fF Inverter Propagation Delay Discharge (pull-down) D t = 0.69R D C OUT = 0.69(10k W )(50fF) = 345 ps Discharge (pull-up) D t = 0.69R U C OUT = 0.69(10k W )(50fF) = 345 ps

Slide 9

V DD A C B V OUT B A C Logic is Complementary and produces F = A + (BC) CMOS Logic Gate NMOS and PMOS utilize a similar arrangement of information signs PMOS just in draw up PMOS direct when info is low PMOS don't lead when A +(BC) NMOS just in draw down NMOS direct when information is high. NMOS direct for A + (BC)

Slide 10

V DD A C B V OUT B A C CMOS Logic Gate: Example Inputs A = 0 PMOS all lead B = 0 Output is High C = 0 = V DD NMOS don't lead Logic is Complementary and produces F = 1

Slide 11

V DD A C B V OUT B A C CMOS Logic Gate: Example Inputs A = 0 PMOS A behaviors; B and C Open B = 1 Output is Low C = 1 = 0 NMOS B and C lead; An open Logic is Complementary and produces F = 0

Slide 12

V DD V DD A R D R U R U R U R D R D A C B V OUT C B V OUT B A B A C Switched Equivalent Resistance Network Switches close when information is low. Switches close when info is high.

Slide 13

V DD A R D R U R U R U R D R D C B V OUT B A C OUT = 50 fF C Logic Gate Propagation Delay: Initial State The underlying state relies on upon the old (past) sources of info. Illustration: A=0, B=0, C=0 for quite a while. These sources of info gave a way to V DD for quite a while and the capacitor has precharged up to V DD = 5V.

Slide 14

V DD A R D R D R U R U R D R U This breaks the way from V OUT to V DD C B V OUT And opens a way from V OUT to GND B A C OUT = 50 fF C Logic Gate Propagation Delay: Transient The identical resistance of the draw down or pull-up system for the transient stage relies on upon the new present information state . Case: At t=0, B and C change from low to high (V DD ) and A remaining parts low. C OUT releases through the draw down resistance of doors B and C in arrangement. D t = 0.69(R DB +R DC )C OUT = 0.69(20k W )(50fF) = 690 ps The proliferation deferral is two times longer than that for the inverter!

Slide 15

V DD R D R D R U R U R U R D A Fastest general? C B V OUT Slowest generally? B C OUT = 50 fF A C Logic Gate: Worst Case Scenarios What blend of past and introduce rationale sources of info will make the Pull-Up the speediest ? What mix of past and introduce rationale data sources will make the Pull-Up the slowest ? What blend of past and display rationale information sources will make the Pull-Down the speediest ? What mix of past and display rationale data sources will make the Pull-Down the slowest ?

Slide 16

V DD B2 = V OUT 1 V DD A1 50 fF 50 fF A2 B1 V OUT 1 C2 B2 V OUT 2 B2 A1 B1 A2 C2 Logic Gate Cascade To evade vast resistance because of numerous doors in arrangement, rationale capacities with at least 4 data sources are generally produced using falling at least two 2-4 input pieces. The four free info are A1, B1, A2 and C2. Quickest: A2 high releases door 2 without sitting tight for the yield of entryway 1. Slowest: C2 high and A2 low makes door 2 sit tight for Gate 1 yield