EE466: VLSI Design

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EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs

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Outline Junction Capacitances Parasitic capacitances Velocity Saturation Channel length regulation Threshold Voltage Body impact Subthreshold conduction

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The n + locales shapes various planar pn-intersections with the encompassing p-sort substrate numbered 1-5 on the chart. Planar intersections 2, 3 and 4 are encompassed by the p + channel stop embed. Planar intersection 1 is confronting the channel while the base planar intersection 5 is confronting the p-sort substrate with doping N A . The intersection sorts will be n +/p, n +/p + , n +/p + n +/p + and n +/p. Intersection Capacitances

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Junction Capacitances The voltage subordinate source-substrate and deplete substrate intersection capacitances are because of exhaustion charge encompassing the source or deplete dispersion districts installed in the substrate. The source-substrate and deplete substrate intersections are switch one-sided under ordinary working conditions. The measure of intersection capacitance is a component of connected terminal voltages

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Junction Capacitances All intersections are thought to be sudden. Given that the consumption thickness is xd we can process the exhaustion capacitance of an invert one-sided sudden pn-intersection. Where NA and ND are the n-sort and p-sort doping densities separately, V is the negative turn around predisposition voltage. The inherent intersection potential is:

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The intersection is forward one-sided for a positive voltage V and switch one-sided for a negative voltage V. The exhaustion locale charge put away here as far as x d is A stands for the intersection territory. The intersection capacitance connected with the exhaustion locale is characterized as: If we separate the condition portraying Q j regarding the predisposition voltage we get C j . Intersection Capacitances

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Junction Capacitances We can compose the intersection capacitance If the zero predisposition capacitance is: in a more broad frame as m is the inclination coefficient and is 0.5 for sudden intersections and 1/3 for directly reviewed intersection profiles The estimation of the intersection capacitance at last relies on upon the outside predisposition voltage connected over the pn-intersection.

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The sidewalls of a common MOSFET source or deplete dispersion locale are encompassed by a p + channel stop embed having a higher doping thickness than the substrate doping thickness N A . The sidewall zero predisposition capacitance is C j0sw and will be unique in relation to the beforehand talked about intersection capacitance. The zero-inclination capacitance per unit zone can be found as takes after: Where N A(sw) is the sidewall doping thickness, f 0(sw) is the implicit capability of the sidewall intersections. All sidewalls in an average dispersion structure have roughly a similar intersection profundity x j . The zero inclination sidewall intersection capacitance per unit length is: Junction Capacitances

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Beyond the unfaltering state conduct of the MOS transistor. So as to inspect the transient (AC) reaction of MOSFETs the computerized circuits comprising of MOSFETs we need to decide the nature and measure of parasitic capacitances connected with the MOS transistor. On chip capacitances found on MOS circuits are when all is said in done confused elements of the format geometries and the assembling forms. The greater part of these capacitances are not lumped but rather appropriated and their correct counts would normally require complex three dimensional nonlinear charge-voltage models. A lumped representation of the capacitance can be utilized to break down the dynamic transient conduct of the gadget. The capacitances can be named oxide related or intersection capacitances and we will begin the investigation with the oxide related capacitances. MOS Capcitances

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These are C gs and C gd individually. In the event that both the source and deplete locales have a similar width (W), the cover capacitance gets to be: C gs =C bull WL D and C gd =C bull WL D . These cover capacitances are voltage subordinate. C gs , C gd and C gb are voltage reliant and dispersed They result from the association between the door voltage and the channel charge. D C db C gd G B C sb C gs S MOS Capacitances C gb Masks result in a few areas having covers, for instance the entryway terminal covers both the source and deplete districts at the edges. Two cover capacitances emerge thus.

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MOS Capacitance Model Simply saw as parallel plate capacitor Gate-Oxide-Channel C = C g = e bull WL/t bull = C bull WL Define Cpermicron = C bull L = e bull L/t bull

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The door to-source capacitance is really the entryway to-channel capacitance seen between the door and the source terminals. The entryway to-deplete capacitance is really the door to-channel capacitance seen between the door and the deplete terminals. In Cut-off mode the surface is not rearranged and there is no directing channel connecting the surface to the source and to the deplete. The door to-source and entryway to-deplete capacitances are both equivalent to zero (C gs =C gd =0). The door to-substrate capacitance can be approximated by: C gb =C bull WL In direct mode the modified channel reaches out over the MOSFET between the source and deplete. This directing reversal layer at first glance viably shields the substrate from the entryway electric field making it C gb =0. MOS Oxide Capacitances

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In straight mode the conveyed door to-channel capacitance perhaps saw as being shared similarly between the source and the deplete prompting to: C gs =C gd =0.5C bull WL If the MOSFET is working in immersion mode the reversal layer at first glance does not stretch out to the deplete, but rather is squeezed off. The door to-deplete capacitance in subsequently zero (C gd =0). The source is however still connected to the leading channel. It shields the entryway from the channel prompting to C gb of zero. The circulated entryway to-channel capacitance as observed between the door and the source is approximated by: C gs 2/3C bull WL. MOSFET Oxide Capacitance

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MOS Gate Capacitances

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Velocity Saturation Ideal bearer speed connection: v = mE E = Vds/L in all actuality speed does not increment always with connected field For high estimations of Applied field, E ~ 10000V/cm v= mE/(1+E/Esat)

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Velocity Saturation and Mobility Degradation Recall perfect current condition With speed soaked at v=vsat

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Velocity Saturated Current Modeling Cutoff Ids = 0: Vgs<Vt Linear Ids = IdsatVds/Vdsat: Vds<Vdsat Saturation Ids = Idsat: Vds>Vdsat Modeling with observational parameters α between 2(ideal) to 1(compeletely speed immersed

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Velocity Saturation The basic E-field at which disseminating impacts happen relies on upon the doping levels and the vertical electric field connected. Speed immersion impacts are less declared in pMOS gadgets. By expanding V DS the electrical field in the channel at last achieves the basic esteem and the bearers at the deplete get to be speed immersed. Advance expanding V DS does not bring about expanded I D . The current soaks at I DSAT The conduct of the MOS transistor is better comprehended by investigation of the I-V bends.

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