332:479 Concepts in VLSI Design Lecture 5 MIPS Processor Example

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Ideas in VLSI Des. Lec. 5. Slide 2. 3/3/2012. Layout. Outline PartitioningMIPS Processor ExampleArchitectureMicroarchitectureLogic DesignCircuit DesignPhysical DesignFabrication, Packaging, TestingSummary. Material from: CMOS VLSI Design,by Weste and Harris, Addison-Wesley, 2005. Ideas in VLSI Des. Lec. 5.

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332:479 Concepts in VLSI Design Lecture 5 MIPS Processor Example David Harris Harvey Mudd College Spring 2004

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Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design Circuit Design Physical Design Fabrication, Packaging, Testing Summary Material from: CMOS VLSI Design , by Weste and Harris, Addison-Wesley, 2005 Concepts in VLSI Des. Lec. 5

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Coping with Complexity How to plan System-on-Chip? A large number (soon billions!) of transistors Tens to many architects Structured Design Partitioning Concepts in VLSI Des. Lec. 5

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Structured Design Hierarchy : Divide and Conquer Recursively framework into modules Regularity Reuse modules wherever conceivable Ex: Standard cell library Modularity : very much shaped interfaces Allows modules to be dealt with as secret elements Locality Physical and transient Concepts in VLSI Des. Lec. 5

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Abstraction Levels Synopsys Behavioral Simulation Synopsys Design Analyzer ARCHITECTURE & BEHAVIORAL REGISTER TRANSFER – Verilog/VHDL LOGIC SWITCH LEVEL CIRCUIT (TRANSISTORS) LAYOUT & TEST PATTERNS FABRICATION LINE Envisia Standard Cell Place-and-Route Cadence Verilog-XL Synopsys Logic Sim. Dracula Logic versus Format Assura Circuit Extractor SPICE and Cadence Specter Spectral Test Pattern Gen. Rhythm LayoutPlus SUPREM Concepts in VLSI Des. Lec. 5

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Design Partitioning Architecture : User's point of view, what does it do? Guideline set, registers MIPS, x86, Alpha, PIC, ARM, … Microarchitecture Single cycle, multcycle, pipelined, superscalar? Rationale : how are utilitarian pieces built Ripple convey, convey lookahead, convey select adders Circuit : how are transistors utilized Complementary CMOS, pass transistors, domino Physical : chip design Datapaths, recollections, arbitrary rationale Concepts in VLSI Des. Lec. 5

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Gajski Y-Chart Concepts in VLSI Des. Lec. 5

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MIPS Architecture Example: subset of MIPS processor engineering Drawn from Patterson & Hennessy MIPS is a 32-bit design with 32 registers Consider 8-bit subset utilizing 8-bit datapath Only actualize 8 registers ($0 - $7) $0 hardwired to 00000000 8-bit program counter You'll fabricate this processor in the labs Illustrate the key ideas in VLSI outline Concepts in VLSI Des. Lec. 5

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Instruction Set Concepts in VLSI Des. Lec. 5

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Instruction Encoding 32-bit guideline encoding Requires four cycles to get on 8-bit datapath Concepts in VLSI Des. Lec. 5

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Fibonacci (C) f 0 = 1; f - 1 = - 1 f n = f n-1 + f n-2 f = 1, 1, 2, 3, 5, 8, 13, … Concepts in VLSI Des. Lec. 5

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Fibonacci (Assembly) 1 st proclamation: n = 8 How would we make an interpretation of this to gathering? Ideas in VLSI Des. Lec. 5

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Fibonacci (Assembly) Concepts in VLSI Des. Lec. 5

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Fibonacci (Binary) 1 st articulation: addi $3, $0, 8 How would we make an interpretation of this to machine dialect? Imply: utilize direction encodings beneath Concepts in VLSI Des. Lec. 5

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Fibonacci (Binary) Machine dialect program Concepts in VLSI Des. Lec. 5

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MIPS Microarchitecture Multicycle m engineering from Patterson & Hennessy Concepts in VLSI Des. Lec. 5

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Multicycle Controller Concepts in VLSI Des. Lec. 5

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Logic Design Start at top level Hierarchically deteriorate MIPS into units Top-level interface Concepts in VLSI Des. Lec. 5

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Block Diagram Concepts in VLSI Des. Lec. 5

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Hierarchical Design Concepts in VLSI Des. Lec. 5

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HDLs Hardware Description Languages Widely utilized as a part of rationale outline Verilog and VHDL Describe equipment utilizing code Document rationale capacities Simulate rationale before building Synthesize code into doors and design Requires a library of standard cells Concepts in VLSI Des. Lec. 5

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Verilog Example module fulladder( input a, b, c, yield s, cout); sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule module convey( input a, b, c, yield cout) appoint cout = (a&b) | (a&c) | (b&c); endmodule Concepts in VLSI Des. Lec. 5

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Circuit Design How ought to rationale be executed? NANDs and NORs versus ANDs and ORs? Fan-in and fan-out? How wide ought to transistors be? These decisions influence speed, territory, control Logic amalgamation settles on these decisions for you sufficiently good for some applications Hand-created circuits are still better Concepts in VLSI Des. Lec. 5

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Example: Carry Logic dole out cout = (a&b) | (a&c) | (b&c); Transistors? Entryway Delays? Ideas in VLSI Des. Lec. 5

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Example: Carry Logic appoint cout = (a&b) | (a&c) | (b&c); Transistors? Entryway Delays? Ideas in VLSI Des. Lec. 5

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Example: Carry Logic dole out cout = (a&b) | (a&c) | (b&c); Transistors? Door Delays? Ideas in VLSI Des. Lec. 5

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Gate-Level Netlist module convey( input a, b, c, yield cout) wire x, y, z; and g1(x, a, b); and g2(y, a, c); and g3(z, b, c); or g4(cout, x, y, z); endmodule Concepts in VLSI Des. Lec. 5

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Transistor-Level Netlist module convey( input a, b, c, yield cout) wire i1, i2, i3, i4, cn; tranif1 n1(i1, 0, a); tranif1 n2(i1, 0, b); tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn, i2, a); tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn); endmodule Concepts in VLSI Des. Lec. 5

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SPICE Netlist . SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN An I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P MP2 I3 B VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD PMOS W=2U L=0.18U AD=0.3P AS=1P MP5 CN An I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF . Closes Concepts in VLSI Des. Lec. 5

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Physical Design Floorplan Standard cells Place & course Datapaths Slice arranging Area estimation Concepts in VLSI Des. Lec. 5

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MIPS Floorplan Concepts in VLSI Des. Lec. 5

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MIPS Layout Concepts in VLSI Des. Lec. 5

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Standard Cells Uniform cell tallness Uniform well stature M1 V DD and GND rails M2 Access to I/Os Well/substrate taps Exploits consistency Concepts in VLSI Des. Lec. 5

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Synthesized Controller Synthesize HDL into door level netlist Place & Route utilizing standard cell library Concepts in VLSI Des. Lec. 5

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Pitch Matching Synthesized controller region is for the most part wires Design is littler if wires gone through/over cells Smaller = quicker, bring down power too! Configuration snap-together cells for datapaths and exhibits Plan wires into cells Connect by projection Exploits territory Takes bunches of exertion Concepts in VLSI Des. Lec. 5

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MIPS Datapath 8-bit datapath worked from 8 bitslices (normality) Zipper at top drives control signs to datapath Concepts in VLSI Des. Lec. 5

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Slice Plans Slice get ready for bitslice Cell requesting, measurements, wiring tracks Arrange cells for wiring region Concepts in VLSI Des. Lec. 5

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MIPS ALU Arithmetic/Logic Unit is a piece of bitslice Concepts in VLSI Des. Lec. 5

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Area Estimation Need territory evaluations to make floorplan Compare to another piece you effectively composed Or gauge from transistor numbers Budget space for vast wiring tracks Your mileage may differ! Ideas in VLSI Des. Lec. 5

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Design Verification Fabrication is moderate & costly MOSIS 0.6 m: $1000, 3 months State of workmanship: $1M, 1 month Debugging chips is hard Limited perceivability into operation Prove configuration is just before building! Rationale reenactment Ckt. reenactment/formal confirmation Layout versus schematic examination Design & electrical lead checks Verification is > half of exertion on generally chips! Ideas in VLSI Des. Lec. 5

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Technology CAD Design Rule Checker Electrical Rule Checker Circuit Extraction from format Logic versus format check Concepts in VLSI Des. Lec. 5

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Fabrication & Packaging Tapeout last design Fabrication 6, 8, 12" wafers Optimized for throughput, not inertness (10 weeks!) Cut into individual dice Packaging Bond gold wires from kick the bucket I/O cushions to bundle Concepts in VLSI Des. Lec. 5

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Testing Test that chip works Design blunders Manufacturing mistakes A solitary tidy molecule or wafer imperfection murders a kick the bucket Yields from 90% to < 10% Depends on pass on size, development of process Test each part before transportation to client Concepts in VLSI Des. Lec. 5

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Summary Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design Circuit Design Physical Design Fabrication, Packaging, Testing Concepts in VLSI Des. Lec. 5

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